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| 型号： | PSD713S5 |
| 英文描述： | Field Programmable Microcontroller Peripherals with Supervisory Functions(可编程逻辑，4K位SRAM,27个可编程I/O,通用PLD有66个输入) |
| 中文描述： | 现场可编程微控制器外围设备具有监督职能（可编程逻辑，4K的位的SRAM，27余个可编程输入/输出，通用PLD的有66个输入） |
| 文件页数： | 6/104页 |
| 文件大小： | 515K |
| 代理商： | PSD713S5 |
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PSD7XX Family
13-6
The following table describes the pin names and pin functions of the PSD7XX. Pins that
have multiple names and/or functions are defined by configuration.
Table 2.
PSD7XX Pin
Descriptions
Pin Name
Pin
Type
Function Description
ADIO0–7
30–37
I/O
Address/Data Port, interface to Microcontroller Bus
1. Input pins for multiplexed low order address/data byte.
ALE or AS latches address A0-7. The PSD drives data
out only if read is active and one of the internal PSD
functional blocks is selected.
2. Address A0-7 inputs for non-multiplexed bus or 80C251
mode
3. A4/D0-A11/D7 inputs in 80C51XA mode
4. Address (or latched address) inputs to PLD
ADIO8–15
39–46
I/O
Address/Data Port, interface to Microcontroller Bus
1. Address A8-15 inputs in 8-bit data bus mode, or as
multiplexed high order address/data byte inputs in 16-bit
data bus mode. ALE or AS latches address A8-15.
The PSD drives data out only if read is active and one of
the internal PSD functional blocks is selected.
2. Address A8-15 inputs in non-multiplexed bus mode
3. AD8-AD15 inputs in 80C251 mode
4. A12-A19 or A12/D8 - A19/D15 inputs in 80C51XA mode
5. Address (or latched address) inputs to PLD
CNTL0)
47
I
Write Input pin with multiple configurations. Depending on
the MCU interface selected, this pin can be:
1. WR – active low write input
2. R_W – read/write pin, low for write bus cycle
3. WRL – for 16 bit data bus only, write to low byte, active low
4. Control signal (CNTL0) input to PLD
(WR,
R_W,
WRL)
CNTL1
50
I
Read or Data Strobe Input pin with multiple configurations.
Depending on the MCU interface selected, this pin can be:
1. RD – active low read input
2. E – E clock input.
During a write bus cycle, E is high and R/W is low
During a read bus cycle, E is high and R/W is high
3. DS – Data Strobe, active low
4. LDS – Strobe for low data byte, 16-bit data bus mode,
active low
5. PSEN – Program Select Enable, active low in read bus
cycle (80C251 configuration)
6. Control signal (CNTL1) input to PLD
(RD,
E,
DS,
LDS,
PSEN)
CNTL2
49
I
Read or other Control input pin with multiple configurations.
Depending on the MCU interface selected, this pin can be:
1. PSEN – Program Select enable, active low in code fetch
bus cycle
2. BHE – High byte enable, 16-bit data bus
3. UDS – Strobe for high data byte, 16-bit data bus mode,
active low
4. SIZ0 – Byte enable input
5. Control signal (CNTL2) input or general input to PLD
(PSEN,
BHE,
UDS,
SIZ0)
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