参数资料
型号: PSD8133V20MIT
厂商: 意法半导体
英文描述: Flash In-System Programmable ISP Peripherals For 8-bit MCUs
中文描述: Flash在系统可编程ISP的外设的8位微控制器
文件页数: 71/110页
文件大小: 1685K
代理商: PSD8133V20MIT
71/110
PSD813F1
PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE
The JTAG interface on the PSD can be enabled on
Port C (see
Table 34., page 72
). All memory
(Flash and EEPROM), PLD logic, and PSD config-
uration bits may be programmed through the
JTAG interface. A blank part can be mounted on a
printed circuit board and programmed using
JTAG.
The standard JTAG signals (IEEE 1149.1) are
TMS, TCK, TDI, and TDO. Two additional signals,
TSTAT and TERR, are optional JTAG extensions
used to speed up program and erase operations.
Note:
By default, on a blank PSD (as shipped from
factory or after erasure), four pins on Port C are
enabled for the basic JTAG signals TMS, TCK,
TDI, and TDO.
Standard JTAG Signals
The standard JTAG signals (TMS, TCK, TDI, and
TDO) can be enabled by any of three different con-
ditions that are logically ORed. When enabled,
TDI, TDO, TCK, and TMS are inputs, waiting for a
serial command from an external JTAG controller
device (such as FlashLink or Automated Test
Equipment). When the enabling command is re-
ceived from the external JTAG controller, TDO be-
comes an output and the JTAG channel is fully
functional inside the PSD. The same command
that enables the JTAG channel may optionally en-
able the two additional JTAG pins, TSTAT and
TERR.
The following symbolic logic equation specifies the
conditions enabling the four basic JTAG pins
(TMS, TCK, TDI, and TDO) on their respective
Port C pins. For purposes of discussion, the logic
label JTAG_ON will be used. When JTAG_ON is
true, the four pins are enabled for JTAG. When
JTAG_ON is false, the four pins can be used for
general PSD I/O.
JTAG_ON = PSDsoft_enabled +
/* An NVM configuration bit inside the PSD
is set by the designer in the PSDsoft
Express Configuration utility. This
dedicates the pins for JTAG at all
times (compliant with IEEE 1149.1) */
Microcontroller_enabled +
/* The microcontroller can set a bit at run-
time by writing to the PSD register,
JTAG Enable. This register is located
at address CSIOP + offset C7h. Setting
the JTAG_ENABLE bit in this register
will enable the pins for JTAG use. This
bit is cleared by a PSD reset or the
microcontroller. See
Table
35., page 72
for bit definition. */
PSD_product_term_enabled;
/* A dedicated product term (PT) inside the
PSD can be used to enable the JTAG pins.
This PT has the reserved name JTAGSEL.
Once defined as a node in PSDabel, the
designer can write an equation for
JTAGSEL. This method is used when the
Port C JTAG pins are multiplexed with
other I/O signals. It is recommended to
logically tie the node JTAGSEL to the
JEN\ signal on the Flashlink cable when
multiplexing JTAG signals. (AN1153)
The PSD supports JTAG In-System-Configuration
(ISC) commands, but not Boundary Scan. A defi-
nition of these JTAG-ISC commands and se-
quences are defined in a supplemental document
available from ST. ST
s PSDsoft Express software
tool and FlashLink JTAG programming cable im-
plement these JTAG-ISC commands. This docu-
ment is needed only as a reference for designers
who use a FlashLink to program their PSD.
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