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参数资料
型号： PSD814270MIT
厂商： 意法半导体
英文描述： Resonant-Mode Power Supply Controllers 16-SOIC 0 to 70
中文描述： Flash在系统可编程ISP的外设的8位微控制器
文件页数： 51/110页
文件大小： 1737K
代理商： PSD814270MIT
51/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
I/O PORTS
There are four programmable I/O ports: Ports A, B,
C, and D. Each of the ports is eight bits except Port
D, which is 3 bits. Each port pin is individually user
configurable, thus allowing multiple functions per
port. The ports are configured using PSDsoft Ex-
press Configuration or by the MCU writing to on-
chip registers in the CSIOP space.
The topics discussed in this section are:
General Port architecture
Port operating modes
Port Configuration Registers (PCR)
Port Data Registers
Individual Port functionality.
General Port Architecture
The general architecture of the I/O Port block is
shown in
Figure 26., page 52
. Individual Port ar-
chitectures are shown in
Figure 28., page 58
to
Figure 31., page 61
. In general, once the purpose
for a port pin has been defined, that pin is no long-
er available for other purposes. Exceptions are
noted.
As shown in
Figure 26., page 52
, the ports contain
an output multiplexer whose select signals are
driven by the configuration bits in the Control Reg-
isters (Ports A and B only) and PSDsoft Express
Configuration. Inputs to the multiplexer include the
following:
Output data from the Data Out register
Latched address outputs
CPLD macrocell output
External Chip Select (ECS0-ECS2) from the
CPLD.
The Port Data Buffer (PDB) is a tri-state buffer that
allows only one source at a time to be read. The
Port Data Buffer (PDB) is connected to the Internal
Data Bus for feedback and can be read by the
MCU. The Data Out and macrocell outputs, Direc-
tion and Control Registers, and port pin input are
all connected to the Port Data Buffer (PDB).
■
■
■
■
■
■
■
■
■
The Port pin’s tri-state output driver enable is con-
trolled by a two input OR gate whose inputs come
from the CPLD AND Array enable product term
and the Direction Register. If the enable product
term of any of the Array outputs are not defined
and that port pin is not defined as a CPLD output
in the PSDabel file, then the Direction Register has
sole control of the buffer that drives the port pin.
The contents of these registers can be altered by
the MCU. The Port Data Buffer (PDB) feedback
path allows the MCU to check the contents of the
registers.
Ports A, B, and C have embedded Input Macro-
cells (IMC). The Input Macrocells (IMC) can be
configured as latches, registers, or direct inputs to
the PLDs. The latches and registers are clocked
by Address Strobe (ALE/AS, PD0) or a product
term from the PLD AND Array. The outputs from
the Input Macrocells (IMC) drive the PLD input bus
and can be read by the MCU. See the section en-
titled
Input Macrocell, page 41
.
Port Operating Modes
The I/O Ports have several modes of operation.
Some modes can be defined using PSDabel,
some by the MCU writing to the Control Registers
in CSIOP space, and some by both. The modes
that can only be defined using PSDsoft Express
must be programmed into the device and cannot
be changed unless the device is reprogrammed.
The modes that can be changed by the MCU can
be done so dynamically at run-time. The PLD I/O,
Data Port, Address Input, and Peripheral I/O
modes are the only modes that must be defined
before programming the device. All other modes
can be changed by the MCU at run-time. See Ap-
plication Note
AN1171
for more detail.
Table 19., page 53
summarizes which modes are
available on each port.
Table 22., page 56
shows
how and where the different modes are config-
ured. Each of the port operating modes are de-
scribed in the following sections.
相关PDF资料
PDF描述
PSD814270MT Resonant-Mode Power Supply Controllers 16-SOIC 0 to 70
PSD814290JIT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD814290JT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD814290MIT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD814290MT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
相关代理商/技术参数
参数描述
PSD833F2-90J 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
PSD833F2-90JI 功能描述:SPLD - 简单可编程逻辑器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 逻辑系列:TICPAL22V10Z 大电池数量:10 最大工作频率:66 MHz 延迟时间:25 ns 工作电源电压:4.75 V to 5.25 V 电源电流:100 uA 最大工作温度:+ 75 C 最小工作温度:0 C 安装风格:Through Hole 封装 / 箱体:DIP-24
PSD833F2-90M 功能描述:SPLD - 简单可编程逻辑器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 逻辑系列:TICPAL22V10Z 大电池数量:10 最大工作频率:66 MHz 延迟时间:25 ns 工作电源电压:4.75 V to 5.25 V 电源电流:100 uA 最大工作温度:+ 75 C 最小工作温度:0 C 安装风格:Through Hole 封装 / 箱体:DIP-24
PSD833F2-90MI 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
PSD834F2-15M 制造商:STMicroelectronics 功能描述:Flash In-System Programmable Peripherals 52-Pin PQFP
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