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参数资料
型号： PSD814470JIT
厂商： 意法半导体
英文描述： Flash In-System Programmable ISP Peripherals For 8-bit MCUs
中文描述： Flash在系统可编程ISP的外设的8位微控制器
文件页数： 30/110页
文件大小： 1737K
代理商： PSD814470JIT
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
30/110
SECTOR SELECT AND SRAM SELECT
Sector Select (FS0-FS7, CSBOOT0-CSBOOT3)
and SRAM Select (RS0) are all outputs of the
DPLD. They are setup by writing equations for
them in PSDabel. The following rules apply to the
equations for these signals:
1.
Primary Flash memory and secondary Flash
memory Sector Select signals must
not
be
larger than the physical sector size.
2.
Any primary Flash memory sector must
not
be
mapped in the same memory space as
another Flash memory sector.
3.
A secondary Flash memory sector must
not
be
mapped in the same memory space as
another secondary Flash memory sector.
4.
SRAM, I/O, and Peripheral I/O spaces must
not
overlap.
5.
A secondary Flash memory sector
may
overlap a primary Flash memory sector. In
case of overlap, priority is given to the
secondary Flash memory sector.
6.
SRAM, I/O, and Peripheral I/O spaces
may
overlap any other memory sector. Priority is
given to the SRAM, I/O, or Peripheral I/O.
Example
FS0 is valid when the address is in the range of
8000h to BFFFh, CSBOOT0 is valid from 8000h to
9FFFh, and RS0 is valid from 8000h to 87FFh.
Any address in the range of RS0 always accesses
the SRAM. Any address in the range of CSBOOT0
greater than 87FFh (and less than 9FFFh) auto-
matically addresses secondary Flash memory
segment 0. Any address greater than 9FFFh ac-
cesses the primary Flash memory segment 0. You
can see that half of the primary Flash memory seg-
ment 0 and one-fourth of secondary Flash memory
segment 0 cannot be accessed in this example.
Also note that an equation that defined FS1 to any-
where in the range of 8000h to BFFFh would
not
be valid.
Figure
9
shows the priority levels for all memory
components. Any component on a higher level can
overlap and has priority over any component on a
lower level. Components on the same level must
not
overlap. Level one has the highest priority and
level 3 has the lowest.
Memory Select Configuration for MCUs with
Separate Program and Data Spaces
The 8031 and compatible family of MCUs, which
includes the 80C51, 80C151, 80C251, and
80C51XA, have separate address spaces for Pro-
gram memory (selected using Program Select En-
able (PSEN, CNTL2)) and Data memory (selected
using Read Strobe (RD, CNTL1)). Any of the
memories within the PSD can reside in either
space or both spaces.
This is controlled through manipulation of the VM
register that resides in the CSIOP space.
The VM register is set using PSDsoft Express to
have an initial value. It can subsequently be
changed by the MCU so that memory mapping
can be changed on-the-fly.
For example, you may wish to have SRAM and pri-
mary Flash memory in the Data space at Boot-up,
and secondary Flash memory in the Program
space at Boot-up, and later swap the primary and
secondary Flash memories. This is easily done
with the VM register by using PSDsoft Express
Configuration to configure it for Boot-up and hav-
ing the MCU change it when desired.
Table
13., page 31
describes the VM Register.
Figure 9. Priority Level of Memory and I/O
Components
Configuration Modes for MCUs with Separate
Program and Data Spaces
Separate Space Modes.
Program space is sep-
arated from Data space. For example, Program
Select Enable (PSEN, CNTL2) is used to access
the program code from the primary Flash memory,
while Read Strobe (RD, CNTL1) is used to access
data from the secondary Flash memory, SRAM
and I/O Port blocks. This configuration requires
the VM register to be set to 0Ch (see
Figure
10., page 31
).
Combined Space Modes.
The
Data spaces are combined into one memory
space that allows the primary Flash memory, sec-
ondary Flash memory, and SRAM to be accessed
by either Program Select Enable (PSEN, CNTL2)
or Read Strobe (RD, CNTL1). For example, to
configure the primary Flash memory in Combined
space, Bits b2 and b4 of the VM register are set to
'1' (see
Figure 11., page 31
).
Program
and
Level 1
SRAM, I/O, or
Peripheral I/O
Level 2
Secondary
Non-Volatile Memory
Highest Priority
Lowest Priority
Level 3
Primary Flash Memory
AI02867D
相关PDF资料
PDF描述
PSD814470JT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD814470MIT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD814470MT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD814490JT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD814520JT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
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PSD833F2-90JI 功能描述:SPLD - 简单可编程逻辑器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 逻辑系列:TICPAL22V10Z 大电池数量:10 最大工作频率:66 MHz 延迟时间:25 ns 工作电源电压:4.75 V to 5.25 V 电源电流:100 uA 最大工作温度:+ 75 C 最小工作温度:0 C 安装风格:Through Hole 封装 / 箱体:DIP-24
PSD833F2-90M 功能描述:SPLD - 简单可编程逻辑器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 逻辑系列:TICPAL22V10Z 大电池数量:10 最大工作频率:66 MHz 延迟时间:25 ns 工作电源电压:4.75 V to 5.25 V 电源电流:100 uA 最大工作温度:+ 75 C 最小工作温度:0 C 安装风格:Through Hole 封装 / 箱体:DIP-24
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PSD834F2-15M 制造商:STMicroelectronics 功能描述:Flash In-System Programmable Peripherals 52-Pin PQFP
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