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参数资料
型号： PSD814590MT
厂商： 意法半导体
英文描述： Flash In-System Programmable ISP Peripherals For 8-bit MCUs
中文描述： Flash在系统可编程ISP的外设的8位微控制器
文件页数： 66/110页
文件大小： 1737K
代理商： PSD814590MT
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
66/110
PSD Chip Select Input (CSI, PD2)
PD2 of Port D can be configured in PSDsoft Ex-
press as PSD Chip Select Input (CSI). When Low,
the signal selects and enables the internal Flash
memory, EEPROM, SRAM, and I/O blocks for
READ or WRITE operations involving the PSD. A
High on PSD Chip Select Input (CSI, PD2) dis-
ables the Flash memory, EEPROM, and SRAM,
and reduces the PSD power consumption. How-
ever, the PLD and I/O signals remain operational
when PSD Chip Select Input (CSI, PD2) is High.
There may be a timing penalty when using PSD
Chip Select Input (CSI, PD2) depending on the
speed grade of the PSD that you are using. See
the timing parameter t
SLQV
in
Table 61., page 94
or
Table 62., page 95
.
Input Clock
The PSD provides the option to turn off CLKIN
(PD1) to the PLD to save AC power consumption.
CLKIN (PD1) is an input to the PLD AND Array and
the Output Macrocells (OMC).
During Power-down mode, or, if CLKIN (PD1) is
not being used as part of the PLD logic equation,
the clock should be disabled to save AC power.
CLKIN (PD1) is disconnected from the PLD AND
Array or the Macrocells block by setting Bits 4 or 5
to a 1 in PMMR0.
Input Control Signals
The PSD provides the option to turn off the input
control signals (CNTL0, CNTL1, CNTL2, Address
Strobe (ALE/AS, PD0) and DBE) to the PLD to
save AC power consumption. These control sig-
nals are inputs to the PLD AND Array. During
Power-down mode, or, if any of them are not being
used as part of the PLD logic equation, these con-
trol signals should be disabled to save AC power.
They are disconnected from the PLD AND Array
by setting Bits 2, 3, 4, 5, and 6 to a 1 in PMMR2.
Table 32. APD Counter Operation
APD Enable Bit
ALE PD Polarity
ALE Level
APD Counter
0
X
X
Not Counting
1
X
Pulsing
Not Counting
1
1
1
Counting (Generates PDN after 15 Clocks)
1
0
0
Counting (Generates PDN after 15 Clocks)
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PSD833F2-90J 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
PSD833F2-90JI 功能描述:SPLD - 简单可编程逻辑器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 逻辑系列:TICPAL22V10Z 大电池数量:10 最大工作频率:66 MHz 延迟时间:25 ns 工作电源电压:4.75 V to 5.25 V 电源电流:100 uA 最大工作温度:+ 75 C 最小工作温度:0 C 安装风格:Through Hole 封装 / 箱体:DIP-24
PSD833F2-90M 功能描述:SPLD - 简单可编程逻辑器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 逻辑系列:TICPAL22V10Z 大电池数量:10 最大工作频率:66 MHz 延迟时间:25 ns 工作电源电压:4.75 V to 5.25 V 电源电流:100 uA 最大工作温度:+ 75 C 最小工作温度:0 C 安装风格:Through Hole 封装 / 箱体:DIP-24
PSD833F2-90MI 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
PSD834F2-15M 制造商:STMicroelectronics 功能描述:Flash In-System Programmable Peripherals 52-Pin PQFP
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