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参数资料
| 型号： | PSD833390JIT |
| 厂商： | 意法半导体 |
| 英文描述： | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| 中文描述： | Flash在系统可编程ISP的外设的8位微控制器 |
| 文件页数： | 15/110页 |
| 文件大小： | 1737K |
| 代理商： | PSD833390JIT |
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
PSD ARCHITECTURAL OVERVIEW
PSD devices contain several major functional
blocks. Figure
5
shows the architecture of the PSD
device family. The functions of each block are de-
scribed briefly in the following sections. Many of
the blocks perform multiple functions and are user
configurable.
Memory
Each of the memory blocks is briefly discussed in
the following paragraphs. A more detailed discus-
sion can be found in the section entitled
Memory
Blocks, page 19
.
The 1 Mbit or 2 Mbit (128K x 8, or 256K x 8) Flash
memory is the primary memory of the PSD. It is di-
vided into 8 equally-sized sectors that are individ-
ually selectable.
The optional 256 Kbit (32K x 8) secondary Flash
memory is divided into 4 equally-sized sectors.
Each sector is individually selectable.
The optional SRAM is intended for use as a
scratch-pad memory or as an extension to the
MCU SRAM. If an external battery is connected to
Voltage Stand-by (V
STBY
, PC2), data is retained in
the event of power failure.
Each sector of memory can be located in a differ-
ent address space as defined by the user. The ac-
cess times for all memory types includes the
address latching and DPLD decoding time.
Page Register
The 8-bit Page Register expands the address
range of the MCU by up to 256 times. The paged
address can be used as part of the address space
to access external memory and peripherals, or in-
ternal memory and I/O. The Page Register can
also be used to change the address mapping of
sectors of the Flash memories into different mem-
ory spaces for IAP.
PLDs
The device contains two PLDs, the Decode PLD
(DPLD) and the Complex PLD (CPLD), as shown
in Table
3
, each optimized for a different function.
The functional partitioning of the PLDs reduces
power consumption, optimizes cost/performance,
and eases design entry.
The DPLD is used to decode addresses and to
generate Sector Select signals for the PSD inter-
nal memory and registers. The DPLD has combi-
natorial outputs. The CPLD has 16 Output
Macrocells (OMC) and 3 combinatorial outputs.
The PSD also has 24 Input Macrocells (IMC) that
can be configured as inputs to the PLDs. The
PLDs receive their inputs from the PLD Input Bus
and are differentiated by their output destinations,
number of product terms, and macrocells.
The PLDs consume minimal power. The speed
and power consumption of the PLD is controlled
by the Turbo Bit in PMMR0 and other bits in the
PMMR2. These registers are set by the MCU at
run-time. There is a slight penalty to PLD propaga-
tion time when invoking the power management
features.
I/O Ports
The PSD has 27 individually configurable I/O pins
distributed over the four ports (Port A, B, C, and
D). Each I/O pin can be individually configured for
different functions. Ports can be configured as
standard MCU I/O ports, PLD I/O, or latched ad-
dress outputs for MCUs using multiplexed ad-
dress/data buses.
The JTAG pins can be enabled on Port C for In-
System Programming (ISP).
Ports A and B can also be configured as a data
port for a non-multiplexed bus.
MCU Bus Interface
PSD interfaces easily with most 8-bit MCUs that
have either multiplexed or non-multiplexed ad-
dress/data buses. The device is configured to re-
spond to the MCU’s control signals, which are also
used as inputs to the PLDs. For examples, please
see the section entitled
MCU Bus Interface
Examples, page 45
.
Table 3. PLD I/O
Name
Inputs
Outputs
Product
Terms
Decode PLD (DPLD)
73
17
42
Complex PLD (CPLD)
73
19
140
相关PDF资料 |
PDF描述 |
|---|---|
| PSD833490JT | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD833490MIT | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD833490MT | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD8334V15JT | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD8334V15MT | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PSD833F2-90J | 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| PSD833F2-90JI | 功能描述:SPLD - 简单可编程逻辑器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 逻辑系列:TICPAL22V10Z 大电池数量:10 最大工作频率:66 MHz 延迟时间:25 ns 工作电源电压:4.75 V to 5.25 V 电源电流:100 uA 最大工作温度:+ 75 C 最小工作温度:0 C 安装风格:Through Hole 封装 / 箱体:DIP-24 |
| PSD833F2-90M | 功能描述:SPLD - 简单可编程逻辑器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 逻辑系列:TICPAL22V10Z 大电池数量:10 最大工作频率:66 MHz 延迟时间:25 ns 工作电源电压:4.75 V to 5.25 V 电源电流:100 uA 最大工作温度:+ 75 C 最小工作温度:0 C 安装风格:Through Hole 封装 / 箱体:DIP-24 |
| PSD833F2-90MI | 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| PSD834F2-15M | 制造商:STMicroelectronics 功能描述:Flash In-System Programmable Peripherals 52-Pin PQFP |
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