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参数资料
型号： PSD833F2V-12
厂商： 意法半导体
英文描述： Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
中文描述： Flash在系统可编程（ISP）的周边8位MCU，5V的
文件页数： 16/110页
文件大小： 1737K
代理商： PSD833F2V-12
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
16/110
JTAG Port
In-System Programming (ISP) can be performed
through the JTAG signals on Port C. This serial in-
terface allows complete programming of the entire
PSD device. A blank device can be completely
programmed. The JTAG signals (TMS, TCK,
TSTAT, TERR, TDI, TDO) can be multiplexed with
other functions on Port C. Table
4
indicates the
JTAG pin assignments.
In-System Programming (ISP)
Using the JTAG signals on Port C, the entire PSD
device can be programmed or erased without the
use of the MCU. The primary Flash memory can
also be programmed in-system by the MCU exe-
cuting the programming algorithms out of the sec-
ondary memory, or SRAM. The secondary
memory can be programmed the same way by ex-
ecuting out of the primary Flash memory. The PLD
or other PSD Configuration blocks can be pro-
grammed through the JTAG port or a device pro-
grammer. Table
5
indicates which programming
methods can program different functional blocks
of the PSD.
Power Management Unit (PMU)
The Power Management Unit (PMU) gives the
user control of the power consumption on selected
functional blocks based on system requirements.
The PMU includes an Automatic Power-down
(APD) Unit that turns off device functions during
MCU inactivity. The APD Unit has a Power-down
mode that helps reduce power consumption.
The PSD also has some bits that are configured at
run-time by the MCU to reduce power consump-
tion of the CPLD. The Turbo Bit in PMMR0 can be
reset to '0' and the CPLD latches its outputs and
goes to sleep until the next transition on its inputs.
Additionally, bits in PMMR2 can be set by the
MCU to block signals from entering the CPLD to
reduce power consumption. Please see the sec-
tion entitled
POWER MANAGEMENT, page 62
for
more details.
Table 4. JTAG SIgnals on Port C
Table 5. Methods of Programming Different Functional Blocks of the PSD
Port C Pins
JTAG Signal
PC0
TMS
PC1
TCK
PC3
TSTAT
PC4
TERR
PC5
TDI
PC6
TDO
Functional Block
JTAG Programming
Device Programmer
IAP
Primary Flash Memory
Yes
Yes
Yes
Secondary Flash Memory
Yes
Yes
Yes
PLD Array (DPLD and CPLD)
Yes
Yes
No
PSD Configuration
Yes
Yes
No
相关PDF资料
PDF描述
PSD833F2V-15 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
PSD833F2V-20 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
PSD833F2V-70 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
PSD833F2V-90 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
PSD833F3-12 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
相关代理商/技术参数
参数描述
PSD834F2-15M 制造商:STMicroelectronics 功能描述:Flash In-System Programmable Peripherals 52-Pin PQFP
PSD834F2-70J 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 2M 70ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
PSD834F2-70M 功能描述:SPLD - 简单可编程逻辑器件 5.0V 2M 70ns RoHS:否 制造商:Texas Instruments 逻辑系列:TICPAL22V10Z 大电池数量:10 最大工作频率:66 MHz 延迟时间:25 ns 工作电源电压:4.75 V to 5.25 V 电源电流:100 uA 最大工作温度:+ 75 C 最小工作温度:0 C 安装风格:Through Hole 封装 / 箱体:DIP-24
PSD834F2-90J 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
PSD834F2-90JI 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
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