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参数资料
型号： PSD833F2V-90
厂商： 意法半导体
英文描述： Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
中文描述： Flash在系统可编程（ISP）的周边8位MCU，5V的
文件页数： 37/110页
文件大小： 1737K
代理商： PSD833F2V-90
37/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Output Macrocell (OMC)
Eight of the Output Macrocells (OMC) are con-
nected to Ports A and B pins and are named as
McellAB0-McellAB7. The other eight macrocells
are connected to Ports B and C pins and are
named as McellBC0-McellBC7. If an McellAB out-
put is not assigned to a specific pin in PSDabel,
the Macrocell Allocator block assigns it to either
Port A or B. The same is true for a McellBC output
on Port B or C. Table
15
shows the macrocells and
port assignment.
The Output Macrocell (OMC) architecture is
shown in
Figure 16., page 39
. As shown in the fig-
ure, there are native product terms available from
the AND Array, and borrowed product terms avail-
able (if unused) from other Output Macrocells
(OMC). The polarity of the product term is con-
trolled by the XOR gate. The Output Macrocell
(OMC) can implement either sequential logic, us-
ing the flip-flop element, or combinatorial logic.
The multiplexer selects between the sequential or
combinatorial logic outputs. The multiplexer output
can drive a port pin and has a feedback path to the
AND Array inputs.
The flip-flop in the Output Macrocell (OMC) block
can be configured as a D, T, JK, or SR type in the
PSDabel program. The flip-flop’s clock, preset,
and clear inputs may be driven from a product
term of the AND Array. Alternatively, CLKIN (PD1)
can be used for the clock input to the flip-flop. The
flip-flop is clocked on the rising edge of CLKIN
(PD1). The preset and clear are active High inputs.
Each clear input can use up to two product terms.
Table 15. Output Macrocell Port and Data Bit Assignments
Output
Macrocell
Port
Assignment
Native Product Terms
Maximum Borrowed
Product Terms
Data Bit for Loading or
Reading
McellAB0
Port A0, B0
3
6
D0
McellAB1
Port A1, B1
3
6
D1
McellAB2
Port A2, B2
3
6
D2
McellAB3
Port A3, B3
3
6
D3
McellAB4
Port A4, B4
3
6
D4
McellAB5
Port A5, B5
3
6
D5
McellAB6
Port A6, B6
3
6
D6
McellAB7
Port A7, B7
3
6
D7
McellBC0
Port B0, C0
4
5
D0
McellBC1
Port B1, C1
4
5
D1
McellBC2
Port B2, C2
4
5
D2
McellBC3
Port B3, C3
4
5
D3
McellBC4
Port B4, C4
4
6
D4
McellBC5
Port B5, C5
4
6
D5
McellBC6
Port B6, C6
4
6
D6
McellBC7
Port B7, C7
4
6
D7
相关PDF资料
PDF描述
PSD833F3-12 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
PSD833F3-15 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
PSD833F3-20 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
PSD833F3-70 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
PSD833F3-90 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
相关代理商/技术参数
参数描述
PSD834F2-15M 制造商:STMicroelectronics 功能描述:Flash In-System Programmable Peripherals 52-Pin PQFP
PSD834F2-70J 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 2M 70ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
PSD834F2-70M 功能描述:SPLD - 简单可编程逻辑器件 5.0V 2M 70ns RoHS:否 制造商:Texas Instruments 逻辑系列:TICPAL22V10Z 大电池数量:10 最大工作频率:66 MHz 延迟时间:25 ns 工作电源电压:4.75 V to 5.25 V 电源电流:100 uA 最大工作温度:+ 75 C 最小工作温度:0 C 安装风格:Through Hole 封装 / 箱体:DIP-24
PSD834F2-90J 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
PSD834F2-90JI 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
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