- 您现在的位置：买卖IC网 > PDF目录368232 > PSD835F1-20UI (意法半导体) Single Ended Active Clamp/Reset PWM 16-PDIP -40 to 85 PDF资料下载
参数资料
| 型号： | PSD835F1-20UI |
| 厂商： | 意法半导体 |
| 英文描述： | Single Ended Active Clamp/Reset PWM 16-PDIP -40 to 85 |
| 中文描述： | 在8片位微控制器可配置存储系统 |
| 文件页数： | 4/110页 |
| 文件大小： | 570K |
| 代理商： | PSD835F1-20UI |
第1页第2页第3页当前第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页
PSD835G2
PSD8XX Family
J
A simple interface to 8-bit microcontrollers that use either multiplexed or
non-multiplexed busses. The bus interface logic uses the control signals generated by
the microcontroller automatically when the address is decoded and a read or write is
performed. A partial list of the MCU families supported include:
Intel 8031, 80196, 80188, 80C251
Motorola 68HC11 and 68HC16
Philips 8031 and 80C51XA
Zilog Z80, Z8 and Z180
Infineon C500 family
J
4 Mbit Flash memory. This is the main Flash memory. It is divided into eight
equal-sized blocks that can be accessed with user-specified addresses.
J
Internal secondary 256 Kbit Flash boot memory. It is divided into four equal-sized
blocks that can be accessed with user-specified addresses. This secondary memory
brings the ability to execute code and update the main Flash
concurrently.
J
64 Kbit SRAM. The SRAM’s contents can be protected from a power failure by
connecting an external battery.
J
CPLD with 16 Output Micro
Cells (OMCs) and 24 Input Micro
Cells (IMCs). The
CPLD may be used to efficiently implement a variety of logic functions for internal
and external control. Examples include state machines, loadable shift registers, and
loadable counters. The CPLD can also generate eight external chip selects.
J
Decode PLD (DPLD) that decodes address for selection of internal memory blocks.
J
52 individually configurable I/O port pins that can be used for the following functions:
MCU I/Os
PLD I/Os
Latched MCU address output
Special function I/Os.
I/O ports may be configured as open-drain outputs.
J
Standby current as low as 50 μA for 5 V devices.
J
Built-in JTAG compliant serial port allows full-chip In-System Programmability (ISP).
With it, you can program a blank device or reprogram a device in the factory or the field.
J
Internal page register that can be used to expand the microcontroller address space
by a factor of 256.
J
Internal programmable Power Management Unit (PMU) that supports a low power
mode called Power Down Mode. The PMU can automatically detect a lack of
microcontroller activity and put the PSD8XX into Power Down Mode.
J
Erase/Write cycles:
Flash memory – 100,000 minimum
PLD – 1,000 minimum
2.0
Key Features
3
3.0 PSD8XX
Series
Part #
Flash
Main
Memory
Kbit
8 Sectors
Flash
Serial ISP
JTAG/ISP
Port
Boot
Memory
Kbit
(4 Sectors)
PSD8XX
Series
I/O
Pins
PLD
Inputs Macrocells Macrocells Outputs
Input
Output
PLD
SRAM
Kbit
Supply
Voltage
Device
PSD835G2
PSD813F2
PSD834F2
PSD833F2
52
27
27
27
24
24
24
24
16
16
16
16
24
19
19
19
Yes
Yes
Yes
Yes
4096
1024
2048
1024
256
256
256
256
64
16
64
64
5V
5V
5V
5V
PSD8XX
57
57
57
Table 1. PSD8XX Product Matrix
相关PDF资料 |
PDF描述 |
|---|---|
| PSD835F1-70B81 | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD835F1-70B81I | Single Ended Active Clamp/Reset PWM 16-SOIC -40 to 85 |
| PSD835F1-70J | Single Ended Active Clamp/Reset PWM 16-SOIC -40 to 85 |
| PSD835F1-70JI | Single Ended Active Clamp/Reset PWM 16-SOIC -40 to 85 |
| PSD835F1-70M | Single Ended Active Clamp/Reset PWM 16-SOIC -40 to 85 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PSD835G2-70U | 功能描述:静态随机存取存储器 5.0V 4M 70ns RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| PSD835G2-90U | 功能描述:静态随机存取存储器 5.0V 4M 90ns RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| PSD835G2-90UI | 功能描述:静态随机存取存储器 5.0V 4M 90ns RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| PSD835G2V-12UI | 功能描述:静态随机存取存储器 3.0V 4M 120ns RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| PSD835G2V-90U | 功能描述:静态随机存取存储器 3.0V 4M 90ns RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
发布紧急采购，3分钟左右您将得到回复。