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参数资料
型号： PSD835G3V-B-20M
厂商： 意法半导体
英文描述： Configurable Memory System on a Chip for 8-Bit Microcontrollers
中文描述： 在8片位微控制器可配置存储系统
文件页数： 14/110页
文件大小： 570K
代理商： PSD835G3V-B-20M
PSD835G2
PSD8XX Family
13
8.0
Register Bit
Definition
(cont.)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IMcell7
IMcell6
IMcell5
IMcell4
IMcell3
IMcell2
IMcell1
IMcell0
Input Micro
Cells – Ports A, B and C
Bit definitions: Read Only Registers
Read Input Micro
Cell[7:0] status on Ports A, B and C.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mcella7
Mcella6
Mcella5
Mcella4
Mcella3
Mcella2
Mcella1
Mcella0
Output Micro
Cells A Register
Bit definitions:
Write Register:
Load Micro
CellA[7:0] with 0 or 1.
Read Register:
Read Micro
CellA[7:0] output status.
Output Micro
Cells B Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mcellb7
Mcellb6
Mcellb5
Mcellb4
Mcellb3
Mcellb2
Mcellb1
Mcellb0
Bit definitions:
Write Register:
Load Micro
CellB[7:0] with 0 or 1.
Read Register:
Read Micro
CellB[7:0] output status.
Mask Micro
Cells A Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mcella7
Mcella6
Mcella5
Mcella4
Mcella3
Mcella2
Mcella1
Mcella0
Bit definitions:
Register Bit <j> to 0 = allow Micro
CellA<j> flip flop to be loaded by MCU (default).
Register Bit <j> to 1 = does not allow Micro
CellA<j> flip flop to be loaded by MCU.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mcellb7
Mcellb6
Mcellb5
Mcellb4
Mcellb3
Mcellb2
Mcellb1
Mcellb0
Mask Micro
Cells B Register
Bit definitions:
Register Bit <j> to 0 = allow Micro
CellB<j> flip flop to be loaded by MCU (default).
Register Bit <j> to 1 = does not allow Micro
CellB<j> flip flop to be loaded by MCU.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Sec7_Prot
Sec6_Prot
Sec5_Prot
Sec4_Prot
Sec3_Prot
Sec2_Prot
Sec1_Prot Sec0_Prot
Flash Protection Register
Bit definitions: Read Only Register
Sec<i>_Prot
1 = Flash Sector <i> is write protected.
Sec<i>_Prot
0 = Flash Sector <i> is not write protected.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Security_Bit
*
*
*
Sec3_Prot
Sec2_Prot
Sec1_Prot Sec0_Prot
Flash Boot Protection Register
Bit definitions:
Sec<i>_Prot
Sec<i>_Prot
1 = Boot Block Sector <i> is write protected.
0 = Boot Block Sector <i> is not write protected.
Security_Bit
0 = Security Bit in device has not been set.
1 = Security Bit in device has been set.
相关PDF资料
PDF描述
PSD835G3V-B-20MI Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835G3V-B-20U Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835G3V-B-20UI Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835G3V-B-70B81 Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835G3V-B-70B81I Configurable Memory System on a Chip for 8-Bit Microcontrollers
相关代理商/技术参数
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PSD853F2-90J 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
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PSD853F2-90M 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
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