参数资料
型号: PSD933215JT
厂商: 意法半导体
英文描述: Flash In-System Programmable ISP Peripherals For 8-bit MCUs
中文描述: Flash在系统可编程ISP的外设的8位微控制器
文件页数: 41/110页
文件大小: 1737K
代理商: PSD933215JT
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
36/110
Complex PLD (CPLD)
The CPLD can be used to implement system logic
functions, such as loadable counters and shift reg-
isters, system mailboxes, handshaking protocols,
state machines, and random logic. The CPLD can
also be used to generate three External Chip Se-
lect (ECS0-ECS2), routed to Port D.
Although External Chip Select (ECS0-ECS2) can
be produced by any Output Macrocell (OMC),
these three External Chip Select (ECS0-ECS2) on
Port D do not consume any Output Macrocells
(OMC).
As shown in Figure 13., page 34, the CPLD has
the following blocks:
24 Input Macrocells (IMC)
16 Output Macrocells (OMC)
Macrocell Allocator
Product Term Allocator
AND Array capable of generating up to 137
product terms
Four I/O Ports.
Each of the blocks are described in the sections
that follow.
The Input Macrocells (IMC) and Output Macrocells
(OMC) are connected to the PSD internal data bus
and can be directly accessed by the MCU. This
enables the MCU software to load data into the
Output Macrocells (OMC) or read data from both
the Input and Output Macrocells (IMC and OMC).
This feature allows efficient implementation of sys-
tem logic and eliminates the need to connect the
data bus to the AND Array as required in most
standard PLD macrocell architectures.
Figure 15. Macrocell and I/O Port
I/O PORTS
CPLD MACROCELLS
INPUT MACROCELLS
LATCHED
ADDRESS OUT
MUX
M
UX
D
Q
G
D
QD
WR
PDR
DATA
PRODUCT TERM
ALLOCATOR
DIR
REG.
SELECT
INPUT
PRODUCT TERMS
FROM OTHER
MACROCELLS
POLARITY
SELECT
UP TO 10
PRODUCT TERMS
CLOCK
SELECT
PR
DI LD
D/T
CK
CL
Q
D/T/JK FF
SELECT
PT CLEAR
PT
CLOCK
GLOBAL
CLOCK
PT OUTPUT ENABLE (OE)
MACROCELL FEEDBACK
I/O PORT INPUT
ALE/AS
PT INPUT LATCH GATE/CLOCK
MCU LOAD
PT PRESET
MCU DATA IN
COMB.
/REG
SELECT
MACROCELL
TO
I/O PORT
ALLOC.
CPLD
OUTPUT
TO OTHER I/O PORTS
PLD
INPUT
BUS
PLD
INPUT
BUS
MCU ADDRESS / DATA BUS
MACROCELL
OUT TO
MCU
DATA
LOAD
CONTROL
AND
ARRAY
CPLD OUTPUT
I/O PIN
AI02874
相关PDF资料
PDF描述
PSD933215MIT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD933215MT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD933220JIT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
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