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参数资料
型号： PSD9543V15MIT
厂商： 意法半导体
英文描述： Non-Equalized 2:1 Switch w/ Advanced Technology & Integrated Pullups + Integrated 8kV Contact ESD + Integrated Side Band Signal Switch
中文描述： Flash在系统可编程ISP的外设的8位微控制器
文件页数： 36/110页
文件大小： 1737K
代理商： PSD9543V15MIT
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
36/110
Complex PLD (CPLD)
The CPLD can be used to implement system logic
functions, such as loadable counters and shift reg-
isters, system mailboxes, handshaking protocols,
state machines, and random logic. The CPLD can
also be used to generate three External Chip Se-
lect (ECS0-ECS2), routed to Port D.
Although External Chip Select (ECS0-ECS2) can
be produced by any Output Macrocell (OMC),
these three External Chip Select (ECS0-ECS2) on
Port D do not consume any Output Macrocells
(OMC).
As shown in
Figure 13., page 34
, the CPLD has
the following blocks:
24 Input Macrocells (IMC)
16 Output Macrocells (OMC)
Macrocell Allocator
■
■
■
■
Product Term Allocator
AND Array capable of generating up to 137
product terms
Four I/O Ports.
Each of the blocks are described in the sections
that follow.
The Input Macrocells (IMC) and Output Macrocells
(OMC) are connected to the PSD internal data bus
and can be directly accessed by the MCU. This
enables the MCU software to load data into the
Output Macrocells (OMC) or read data from both
the Input and Output Macrocells (IMC and OMC).
This feature allows efficient implementation of sys-
tem logic and eliminates the need to connect the
data bus to the AND Array as required in most
standard PLD macrocell architectures.
■
■
Figure 15. Macrocell and I/O Port
I/O PORTS
CPLD MACROCELLS
INPUT MACROCELLS
LATCHED
ADDRESS OUT
MUX
M
M
M
M
D
D
Q
Q
Q
G
D
Q D
WR
WR
PDR
DATA
PALLOCATOR
DIR
SELECT
INPUT
PFROM OTHER
MACROCELLS
POLARITY
PROUP TO 10
CLOCK
PR
DI LD
D/T
CK
CL
Q
SELECT
PT CLEAR
PT
GLOBAL
PT OUTPUT ENABLE (OE)
MACROCELL FEEDBACK
I/O PORT INPUT
ALE/AS
PT INPUT LATCH GATE/CLOCK
MCU LOAD
PT PRESET
MCU DATA IN
/REG
SELECT
MACTO
IALLOC.
OCPLD
TO OTHER I/O PORTS
P
P
MCU ADDRESS/DATA BUS
MOUT TO
MCU
CDATA
A
CPLD OUTPUT
I/O PIN
AI02874
相关PDF资料
PDF描述
PSD9134V15MIT 3:1 Active HDMI switch with side band signals for sink w/equalization, pre-emphasis, and de-emphasis , 8KV ESD, operating at HDMI Rev. 1.3 spec at 2.5Gbps offering 8-bit, 10-bit & 12-bit deep color resolution
PSD8334V15MIT HDMI 1:1 re-driver w/ equalization, pre-emphasis, and de-emphasis & 6kV HBM ESD protection, operating at HDMI Rev. 1.3 spec at 2.5Gbps offering 8-bit, 10-bit & 12-bit deep color resolution
PSD9334V15MIT 1:2 Active HDMI switch for source w/equalization, pre-emphasis, and de-emphasis with 6KV ESD, operating at HDMI Rev. 1.3 spec at 2.5Gbps offering 8-bit, 10-bit & 12-bit deep color resolution
PSD8534V15MIT 4 Differential Channel 2:1, 3.3V DVI/HDMI Mux/DeMux
PSD9534V15MIT IC DVI/HDMI MUX/DEMUX 48TSSOP
相关代理商/技术参数
参数描述
PSD954F2-90J 功能描述:SPLD - 简单可编程逻辑器件 U 511-PSD854F2-90J RoHS:否 制造商:Texas Instruments 逻辑系列:TICPAL22V10Z 大电池数量:10 最大工作频率:66 MHz 延迟时间:25 ns 工作电源电压:4.75 V to 5.25 V 电源电流:100 uA 最大工作温度:+ 75 C 最小工作温度:0 C 安装风格:Through Hole 封装 / 箱体:DIP-24
PSD954F2-90M 功能描述:SPLD - 简单可编程逻辑器件 U 511-PSD854F2-90M RoHS:否 制造商:Texas Instruments 逻辑系列:TICPAL22V10Z 大电池数量:10 最大工作频率:66 MHz 延迟时间:25 ns 工作电源电压:4.75 V to 5.25 V 电源电流:100 uA 最大工作温度:+ 75 C 最小工作温度:0 C 安装风格:Through Hole 封装 / 箱体:DIP-24
PSD954F2V-90J 功能描述:SPLD - 简单可编程逻辑器件 5.0V 2M 90ns RoHS:否 制造商:Texas Instruments 逻辑系列:TICPAL22V10Z 大电池数量:10 最大工作频率:66 MHz 延迟时间:25 ns 工作电源电压:4.75 V to 5.25 V 电源电流:100 uA 最大工作温度:+ 75 C 最小工作温度:0 C 安装风格:Through Hole 封装 / 箱体:DIP-24
PSD954F2V-90M 功能描述:SPLD - 简单可编程逻辑器件 PQFP-52 3V 2M 90NS RoHS:否 制造商:Texas Instruments 逻辑系列:TICPAL22V10Z 大电池数量:10 最大工作频率:66 MHz 延迟时间:25 ns 工作电源电压:4.75 V to 5.25 V 电源电流:100 uA 最大工作温度:+ 75 C 最小工作温度:0 C 安装风格:Through Hole 封装 / 箱体:DIP-24
PS-DA0104-01 制造商:POWER-SYSTEMS 制造商全称:Power Systems GmbH+Co.KG 功能描述:DC-AC INVERTER UNIT 4 W SINGLE OUTPUTS
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