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参数资料
| 型号： | PSL126-7LIPCD1A |
| 厂商： | POWER-ONE INC |
| 元件分类： | 电源模块 |
| 英文描述： | 1-OUTPUT DC-DC REG PWR SUPPLY MODULE |
| 封装： | METAL, CASE L04, MODULE |
| 文件页数： | 6/16页 |
| 文件大小： | 255K |
| 代理商： | PSL126-7LIPCD1A |
PSL Series Extended Data Sheet
Positive Switching Regulators (Rugged)
REV. APR 26, 2004
Page 14 of 16
Table 11: Crowbar trigger levels
Characteristics
Conditions
12 V
15 V
24 V
36 V
48 V
Unit
min
max
min
max
min
max
min
max
min
max
Vo c
Trigger voltage
Vi min - Vi max
13.5
16
16.5
19
27
31
40
45.5
55
60
V
Io = 0 - Io nom
t s
Delay time
TC min - TC max
1.5
s
C
Crowbar
This option is recommended to protect the load against
power supply malfunction, but it is not designed to sink ex-
ternal currents.
A fixed-value monitoring circuit checks the output voltage
Vo. When the trigger voltage Vo c is reached, the thyristor
crowbar triggers and disables the output. It may be deacti-
vated by removal of the input voltage. In case of a switching
transistor defect, an internal fuse prevents excessive cur-
rent.
Note: As a central overvoltage protection device, the crow-
bar is usually connected to the external load via distributed
inductance of the lines. For this reason, the overvoltage at
the load can temporarily exceed the trigger voltage
Voc. De-
pending on the application, further decentralized over-
voltage protection elements may have to be used addition-
ally. For further information see:
Technical Information: Ap-
plication Notes.
D
Save Data Input Undervoltage Monitor
Note: Output instead of input undervoltage monitor is
available on request (Option D1).
Terminal D and Go– are connected to a normally conduct-
ing field effect transistor (JFET). The switching characteris-
tics of the option D output are shown in fig.:
Definition of Vt
and VH. A 0.5 W Zener diode provides protection against
overvoltages.
Fig. 14
Test circuit with definition of voltage VD and current ID
Fig. 15
Definition of Vt and VH
Vi +
Gi –
Go –
8.2 V
D
VD
+5 V
100 pF
ID
10 k
JFET
Vt
11025
VD
VD high
VD low
Vt
Vi
VH
11026
The voltage
Vt can be externally adjusted with a trim poten-
tiometer by means of a screwdriver. The hysteresis
VH of Vt
is <2%. Terminal D stays low for a minimum time
tlow min, in
order to prevent any oscillation.
Vt can be set to a value
between
Vi min and Vi max. Please note that the JFET be-
comes conductive when
VD increases above 7 V approx.
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