参数资料
型号: PT7A4409L
英文描述: Complete Motion Control Verilog Library
中文描述: T1/E1/0C3系统同步?
文件页数: 1/34页
文件大小: 306K
代理商: PT7A4409L
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Data Sheet
PT7A4402B/4402L
T1/E1 System Synchronizer
PT0100(08/02)
Ver:0
1
Features
Supports AT&T TR62411 Stratum 3, 4 and
Stratum 4 Enhanced for DS1 interfaces and for
ETSI ETS 300 011, TBR 4, TBR 12, and TBR
13 for E1 interfaces
Provides C1.5, C3, C2, C4, C8 and C16 output
clock signals
Provides three kinds of 8kHz ST-BUS framing
signals
Two independent reference inputs
Input reference frequency 1.544MHz, 2.048MHz
or 8kHz selectable
Provides bit error free reference switching and
meets phase slope and MTIE requirements
Normal, Holdover or Free-Run operating modes
available
Automatic reference input impairment monitor
Power supply: 5V (4402B) and 3.3V(4402L)
Applications
Synchronization and timing control for multitrunk
T1 and E1 systems
ST-BUS clock and frame pulse sources
Primary Trunk Rate Converters
Introduction
PT7A4402B/4402L employs a digital phase-locked
loop (DPLL) to provide timing and synchronizing
signals for multitrunk T1 and E1 primary rate
transmission links. The ST-BUS clock and framing
signals are phase-locked to input reference signals
of either 2.048 MHz, 1.544MHz or 8 kHz.
The PT7A4402B/4402L meets the requirements for
AT&T TR62411 Stratum 3, 4 and Stratum 4 En-
hanced, and ETSI ETS 300 011 in jitter tolerance,
jitter transfer, intrinsic jitter, frequency accuracy, hold-
over accuracy, capture range, phase slope and MTIE,
etc.
The PT7A4402B/4402L operates in Manual or Au-
tomatic Mode, and in each of the modes, three oper-
ating states are available: Normal, Holdover and Free-
Run.
Ordering Information
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