参数资料
型号: PT7A7513WEX
厂商: Pericom
文件页数: 3/9页
文件大小: 0K
描述: IC SUPERVISOR 3.08V 8SOIC
标准包装: 1
类型: 简单复位/加电复位
监视电压数目: 1
复位: 低有效
复位超时: 最小为 160 ms
电压 - 阀值: 3.08V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 标准包装
其它名称: PT7A7513WEXDKR
Data Sheet
PT7A7511-15/7521-25/7531-35
μP Supervisor Circuits
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Pin Configuration
PT7A7511P-7515P
PT7A7511W-7515W
8-Pin PDIP/8-Pin SOIC
PT7A7521P-7525P
PT7A7521W-7525W
8-Pin PDIP/8-Pin SOIC
PT7A7531P-7535P
PT7A7531W-7535W
8-Pin PDIP/8-Pin SOIC
MR
V CC
GND
PFI
1
2
3
4
8
7
6
5
WDO
RESET
WDI
PFO
MR
V CC
GND
PFI
1
2
3
4
8
7
6
5
WDO
RESET
WDI
PFO
MR
V CC
GND
PFI
1
2
3
4
8
7
6
5
RESET
RESET
NC
PFO
Top View
Pin Description
Pin
MR
V CC
GND
PFI
PFO
WDI
RESET
WDO
RESET
Type
I
Power
Ground
I
O
I
O
O
O
Description
Manual-Reset: triggers a reset pulse when pulled below 0.8V, active low. It has an internal 250mA pull-
up current and be driven from a TTL or CMOS logic line as well as shorted to ground with a switch.
Supply Voltage.
Ground Reference for all signals.
Power-Fail Voltage Monitor Input. When PFI is less than 1.25V, PFO goes low. Connect PFI to GND
or Vcc when not used.
Power-Fail Output: it gets low and sinks current when PFI is less than 1.25V; otherwise PFO stays high.
Watchdog Input: If WDI remains high or low for 1.6sec, the internal watchdog timer runs out and WDO
goes low. Floating WDI or connecting WDI to a high-impedance three-state buffer disables the watchdog
feature. The internal watchdog timer clears whenever reset is asserted. WDI is three-stated, or WDI sees a
rising or falling edge.
Reset Output pulses: low for 200ms when triggered, and stays low whenever Vcc is below the reset
threshold. It remains low for 200ms after Vcc rises above the reset threshold or MR goes from low to
high. A watchdog timeout will not trigger RESET unless WDO is connected to MR.
Watchdog Output: pulls low when the internal watchdog timer finishes its 1.6sec count and does not go
high again until the watchdog is cleared. WDO also goes low during low-line conditions. Whenever Vcc
is below the reset threshold, WDO stays low; however, unlike RESET, WDO does not have minimum
pulse width. As soon as Vcc rises above the reset threshold, WDO goes high with no delay.
The inverse of RESET, active high. Whenever RESET is high, RESET is low.
PT0082(10/10)
3
Ver: 7
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