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参数资料
| 型号： | PT7A7517 |
| 英文描述： | 20V Single N-Channel HEXFET Power MOSFET in a D2-Pak package |
| 中文描述： | 2.20V复位低有效监控？ |
| 文件页数： | 8/12页 |
| 文件大小： | 54K |
| 代理商： | PT7A7517 |
5
Data Sheet
PT7A7511-7517/7521-7527/7531-7537
P Supervisor Circuits
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PT0082(05/02)
Ver:1
Functional Description
The PT75xx family can assert reset output during power-up,
power-down and brownout conditions for uP system, detect
power failure or low-battery conditions with a 1.25V threshold
detector and have watchdog functions. Refer to Table 2 for
their individual features. The typical application see Figure 4.
Reset Output
The supervisory circuits can assert reset for a microprocessor
during power-up, power-down and brownout to prevent code
execution errors.
On power-up, once V
CC reaches about 1.2V, RESET is a
guaranteed logic low of 0.4V or less. As V
CC rises, RESET stays
low. When V
CC rises above the reset threshold, an internal timer
releases RESET after about 200ms. RESET pulses low whenever
V
CC drops below the reset threshold (brownout condition). If
brownout occurs in the middle of a previously initiated reset
pulse, the pulse continues for at least another 140ms.
On power-down, once V
CC falls below the reset threshold,
RESET stays low and is guaranteed to be 0.4V or less until Vcc
drops below 1V.
The PT7A752x and PT7A753x active-high RESET output is
simply the complement of the RESET output, and is guaranteed
to be valid with V
CC down to 1.2V. Some Ps, such as Intel’s
80C51, require an active-high reset pulse.
Watchdog Timer
The watchdog circuit monitors the P’s activity. If the P does
not toggle the watchdog input (WDI) within 1.6sec and WDI is
not in high impedance, WDO goes low. As long as RESET is
asserted or the WDI input is in high impedance, the watchdog
timer will stay cleared and will not count. As soon as reset is
released and WDI is driven high or low, the timer will start
counting. Pulses as short as 50ns can be detected.
Typically, WDO will be connected to the non-maskable
interrupt input (NMI) of a P. When V
CC drops below the reset
threshold, WDO will go low whether or not the watchdog timer
has timed out yet. Normally this would trigger an NMI
interrupt, but RESET goes low simultaneously, and thus
overrides the NMI interrupt. If WDI is left unconnected, WDO
can be used as a low-line output. Since floating WDI disables
the internal timer, WDO goes low only when V
CC falls below
the reset threshold, thus functioning as a low-line output.
Manual Reset
The manual-reset input (MR) allows reset to be triggered by a
push-button switch. The switch is effectively debounced by
the 140ms minimum reset pulse width. MR is TTL/CMOS
logic compatible, so it can be driven by any logic reset output.
Power-Fail Comparator
The power-fail comparator will send out a Low signal once
detects a voltage lowered than 1.25V. It can be used for various
purposes because its output and non-inverting input are not
internally connected. The inverting input is internally
connected to a 1.25V reference.
Figure 4. Typical Application Circuit
DC Linear
Regulator
Vcc
Supervisory
PFI
Circuit
WDI
P
Vcc
RESET
I/O Line
NMI
Interrupt
IN
OUT
RESET
WDO
PFO
MR
P
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PT7A7521 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:4.63V Reset Active High Supervisor? |
| PT7A7522 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:4.38V Reset Active High Supervisor? |
| PT7A7523 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:3.08V Reset Active High Supervisor? |
| PT7A7524 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:2.93V Reset Active High Supervisor? |
| PT7A7525 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:2.63V Reset Active High Supervisor? |
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