参数资料
型号: PT7C4302WEX
厂商: Pericom
文件页数: 2/13页
文件大小: 0K
描述: IC RTC NVSRAM 8SOIC
标准包装: 1
类型: 时钟/日历
特点: 闰年,NVSRAM,方波输出,涓流充电器
存储容量: 31B
时间格式: HH:MM:SS(12/24 小时)
数据格式: YY-MM-DD-dd
接口: 3 线串口
电源电压: 1.2 V ~ 5.5 V
电压 - 电源,电池: 1.5 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 标准包装
其它名称: PT7C4302WEXDKR
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12-07-0001
PT0225-4
07/04/12
10
PT7C4302
Real-time Clock Module (3-wire Interface)
a)
Trickle Charger Select
Control the selection of the trickle charger.
TCS
Data
Description
Read/
Write
Other patent
Disable the trickle charger
* Default 0101
1010
Enable the trickle charger
b)
Diode Select
Select whether one diode or two diodes are connected between VCC2 and VCC1.
DS
Data
Description
Read/
Write
00 or 11
The trickle charger is disabled independently of TCS.
* Default
01
One diode is selected.
10
Two diodes are selected.
c)
Resistor Select
Select whether one diode or two diodes are connected between VCC2 and VCC1.
RS
Data
Description
Read/
Write
00
No resistor.
* Default
01
R1 with typ. 2k
10
R2 with typ. 4k
11
R3 with typ. 8k
Communication
1.
3-wire Interface
a)
Command Byte
Figure 1 Command byte
The command byte is shown in Figure 1. Each data transfer is initiated by a command byte. The MSB (Bit 7) must be a logic 1. If
it is 0, writes to the PT7C4302 will be disabled. Bit 6 specifies clock/calendar data if logic 0 or RAM data if logic 1. Bits 1
through 5 specify the designated registers to be input or output, and the LSB (bit 0) specifies a write operation (input) if logic 0 or
read operation (output) if logic 1. The command byte is always input starting with the LSB (bit 0).
b)
RST and SCL Signal
All data transfers are initiated by driving the RST input high and terminated by driving the RST input low. A clock cycle is a
sequence of a falling edge followed by a rising edge. For data inputs, data must be valid during the rising edge of the clock and
data bits are output on the falling edge of clock. If the RST input is low all data transfer terminates and the SDA pin goes to a high
impedance state. Data transfer is illustrated in Figure 2 and Figure 3. At power-up, RST must be a logic 0 until VCC > 2.0V. Also
SCLK must be at a logic 0 when RST is driven to a logic 1 state.
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