参数资料
型号: PT7C4307PE
厂商: PERICOM SEMICONDUCTOR CORP
元件分类: XO, clock
英文描述: 1 TIMER(S), REAL TIME CLOCK, PDIP8
封装: LEAD FREE, MS-001BA, DIP-8
文件页数: 4/20页
文件大小: 517K
代理商: PT7C4307PE
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PT0206(02/05)
Ver: 0
12
Preliminary Data Sheet
PT7C4307
Real-time Clock Module (I
2C Bus)
b)
Data acknowledge response (ACK signal)
When transferring data, the receiver generates a confirmation response (ACK signal, low active) each time an 8-bit data segment
is received. If there is no ACK signal from the receiver, it indicates that normal communication has not been established. (This
does not include instances where the master device intentionally does not generate an ACK signal.)
Immediately after the falling edge of the clock pulse corresponding to the 8th bit of data on the SCL line, the transmitter releases
the SDA line and the receiver sets the SDA line to low (= acknowledge) level.
After transmitting the ACK signal, if the Master remains the receiver for transfer of the next byte, the SDA is released at the
falling edge of the clock corresponding to the 9th bit of data on the SCL line. Data transfer resumes when the Master becomes the
transmitter.
When the Master is the receiver, if the Master does not send an ACK signal in response to the last byte sent from the slave, that
indicates to the transmitter that data transfer has ended. At that point, the transmitter continues to release the SDA and awaits a
STOP condition from the Master.
SCL from Master
1
2
89
SDA from transmitter
(sending side)
SDA from receiver
(receiving side)
Release SDA
Low active
ACK signal
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