参数资料
型号: PT7M7443LTAE
厂商: PERICOM SEMICONDUCTOR CORP
元件分类: 电源管理
英文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5
封装: LEAD FREE, MO-178AA, SOT-23, 5 PIN
文件页数: 6/11页
文件大小: 542K
代理商: PT7M7443LTAE
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PT0289(07/07)
Ver: 0
4
Preliminary Data Sheet
PT7M7443-52
P Supervisory Circuit
Function Description
Reset Output
The reset output is typically connected to the reset input
of a microprocessor (P). A P’s reset input starts or
restarts the P in a known state. The PT7M7443~7452
P supervisory circuits provide the reset logic to prevent
code-execution errors during power-up, power-down and
brownout conditions (see Figure 8 Typical Operating
Circuit).
/RESET changes from high to low whenever the
monitored voltages (RSTIN or VDD) drop below the reset
threshold voltages. Once VRSTIN and VDD exceed their
respective reset threshold voltages, /RESET remains low
for the reset timeout period and than goes high. /RESET
is one-shot pulsed whenever selected manual reset inputs
are asserted. /RESET stays asserted for the normal reset
timeout period (140ms).
/RESET is guaranteed to be in the proper output logic
state for VDD inputs ≥ 1V.
Manual Reset Input Options
Unlike typical manual reset functions associated with
supervisors, each device in the PT7M7443~ 7452 family
includes at lease one manual reset input, which must be
held logic-low for an extended setup period (6.72 typ)
before the /RESET output asserts. When valid manual reset
input conditions/setup periods are met, the /RESET output
is one-shot pulse asserted low for a fixed reset timeout
period (140ms min). Existing front-panel pushbutton
switches (i.e., power on/off, channel up/down, or mode
select) can be used to drive the manual reset inputs. The
extended manual reset setup period prevents nuisance
system resets during normal front-panel usage or resulting
from inadvertent short-term pushbutton closure.
PT7M7443/7444, PT7M7447/7448, and PT7M7451/7452
include a single manual reset input with extended setup
period (/MR1). The PT7M7445/7446 and PT7M7449/7450
include two manual reset inputs (/MR1 and /MR2) with
extended setup periods. For dual /MR1, /MR2 devices, both
inputs must be held low simultaneously for the extended
setup period (6.72s typ) before the reset output is pulse
asserted. The dual extended setup provides greater protection
from nuisance resets. (For example, the user or service
technician is informed to simultaneously push both the on/off
button and the channel-select button for 6.72s to reset the
system.)
Figure 2 PT7M7443/7444 Manual Reset Timing
6.72s
MR2
RESET
MR1
210ms
Figure 3 PT7M7445/7446/7449/7450 Manual Reset
Timing Diagram
Figure 1 Typical Operating Circuit
相关PDF资料
PDF描述
PT7M7445LTAE 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5
PT7M7443STAE 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5
PT7M7448MTAE 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5
PT7M7450TTAE 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO6
PT7M7446WTAE 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5
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