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参数资料
| 型号： | PTB48600AAZ |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 电源模块 |
| 英文描述： | 2-OUTPUT 85 W DC-DC REG PWR SUPPLY MODULE |
| 封装： | ROHS COMPLIANT, DIP-8 |
| 文件页数： | 7/10页 |
| 文件大小： | 387K |
| 代理商： | PTB48600AAZ |
Application Notes
For technical support and further information visit http://power.ti.com
Configuring the PTB48600 & PTB4850x DC/DC
Converters for DSL Applications
When operated as a pair, the PTB48600 and PTB4850x
converters are specifically designed to provide all the
required supply voltages for powering xDSL chipsets.
The PTB4850x produces two logic voltages. They include
a 3.3-V source for logic and I/O, and a low-voltage for
powering a digital signal processor core. The PTB48600
produces a balanced pair of complementary supply voltages
that is required for the xDSL transceiver ICs. When used
together in these types of applications, the PTB4850x and
PTB48600 may be configured for power-up sequencing,
and also synchronized to a common switch conversion
frequency. Figure 2-1 shows the required cross-connects
between the two converters to enable these two features.
Switching Frequency Synchronization
Unsynchronized, the difference in switch frequency
introduces a beat frequency into the input and output
AC ripple components from the converters. The beat
frequency can vary considerably with any slight variation
in either converter’s switch frequency. This results in a
variable and undefined frequency spectrum for the ripple
waveforms, which would normally require separate filters
at the input of each converter. When the switch frequency
of the converters are synchronized, the ripple components
are constrained to the fundamental and higher. This
simplifies the design of the output filters, and allows a
common filter to be specified for the treatment of input
ripple.
Figure 2-1; Example of PTB4850x & PTB48600 Modules Configured for DSL Applications
–VTCVR
PTB4850xA
+VI
Enable
–VI
VO1
VO2
COM
Sync Out
EN Out
VO2 Adj
PTB48600A
+VI
Enable
–VI
+VO
–VO
COM
Sync In
±VO Adj
VCCIO
VCORE
+VTCVR
–48 V RTN
–48 V
Input
Filter
+
–
Power-Up Sequencing
The desired power-up sequence for the AC7 supply volt-
ages requires that the two logic-level voltages from the
PTB4850x converter rise to regulation prior to the two
complementary voltages that power the transceiver ICs.
This sequence cannot be guaranteed if the PTB4850x
and PTB48600 are allowed to power up independently,
especially if the 48-V input voltage rises relatively slowly.
To ensure the desired power-up sequence, the “EN Out”
pin of the PTB4850x is directly connected to the active-
low “Enable” input of the PTB48600 (see Figure 2-1).
This allows the PTB4850x to momentarily hold off the
outputs from the PTB48600 until the logic-level voltages
have risen first. Figure 2-2 shows the power-up wave-
forms of all four supply voltages from the schematic of
Figure 2-1.
Figure 2-2; Power-Up Sequencing Waveforms
PTB48600 & PTB4850x
V
(1 V/Div)
V
(1 V/Div)
CORE
CCIO
+V
(5 V/Div)
–V
(5 V/Div)
TCVR
HORIZ SCALE: 10 ms/Div
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