参数资料
型号: PTV12010WAD
厂商: TEXAS INSTRUMENTS INC
元件分类: 电源模块
英文描述: 1-OUTPUT DC-DC REG PWR SUPPLY MODULE
封装: ROHS COMPLIANT, SIP-8
文件页数: 16/22页
文件大小: 386K
代理商: PTV12010WAD
www.ti.com
ELECTRICAL CHARACTERISTICS
SLTS234B – DECEMBER 2004 – REVISED FEBRUARY 2007
operating at 25°C free-air temperature, V
I = 12 V, VO = 3.3 V, C1 = 100 F, C2 = 10 F, C3 = 0 F, and IO = IO max (unless
otherwise noted)
PTV12010W
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
IO
Output current
Natural convection airflow
0
8 (1)
A
VI
Input voltage range
Over IO load range
10.8
13.2
V
Set-point voltage tolerance
±2% (2)
Temperature variation
–40°C < TA < 85°C
±0.5%
Line regulation
Over VI range
±10
mV
VO
Load regulation
Over IO range
±12
mV
Total output variation
Includes set-point, line, load, –40°C
≤ T
A≤ 85°C
±3 (2)
%Vo
Adjust range
Over VI range
1.2
5.5
V
RSET = 280 , VO = 5 V
92%
RSET = 2.0 k, VO = 3.3 V
90%
RSET = 4.32 k, VO = 2.5 V
88%
η
Efficiency
IO = IO max
RSET = 11.5 k, VO = 1.8 V
85%
RSET = 24.3 k, VO = 1.5 V
83%
RSET = open cct., VO = 1.2 V
80%
Output voltage ripple
20-MHz bandwidth
20
mVPP
(peak-to-peak)
IO (trip)
Overcurrent threshold
Reset, followed by auto-recovery
16
A
1-A/s load step, 50 to 100% IO max, C3 = 100 F
Transient response
Recovery time
70
s
Vo over/undershoot
100
mV
IIL Input low current
Pin to GND
–0.13
mA
Track control (pin 5)
Control slew-rate limit
C3
≤ C3 (max)
1
V/ms
VI increasing
9.5
10.4
UVLO
Undervoltage lockout
V
VI decreasing
8.8
9
VIH Input high voltage
Open (3)
Referenced to GND
V
Inhibit control (pin 7)
VIL Input low voltage
–0.2
0.6
IIL Input low current
Pin to GND
–0.24
mA
II (stby)
Input standby current
Inhibit (pin 7) to GND, Track (pin 5) open
10
mA
S
Switching frequency
Over VI and IO ranges
250
325
400
kHz
Nonceramic (C1)
100 (4)
External input capacitance
F
Ceramic (C2)
10 (4)
Nonceramic
0
100 (5)
3,300 (6)
Capacitance value
F
External output capacitance (C3)
Ceramic
0
300
Equivalent series resistance (nonceramic)
4 (7)
m
Per Telcordia SR-332, 50% stress, TA = 40°C, ground
MTBF
Reliability
5
106 Hrs
benign
(1)
See thermal derating curves for safe operating area (SOA), or consult factory for appropriate derating.
(2)
The set-point voltage tolerance is affected by the tolerance and stability of RSET. The stated limit is unconditionally met if RSET has a
tolerance of 1%, with 100 ppm/°C or better temperature stability.
(3)
This control pin is pulled up to an internal supply voltage. To avoid risk of damage to the module, do not apply an external voltage
greater than 7 V. If this input is left open-circuit, the module operates when input power is applied. A small low-leakage (<100 nA)
MOSFET is recommended for control. For further information, consult the related application note.
(4)
A 10-F high-frequency ceramic capacitor and 100-F electrolytic input capacitor are required for proper operation. The electrolytic
capacitor must be rated for the minimum ripple current rating. See the application information for further guidance on input capacitor
selection.
(5)
An external output capacitor is not required for basic operation. Adding 100 F of distributed capacitance at the load improves the
transient response.
(6)
This is the calculated maximum. The minimum ESR limitation often results in a lower value. See the application information for further
guidance.
(7)
This is the typical ESR for all the electrolytic (nonceramic) output capacitance. Use 7 m
as the minimum when using max-ESR values
to calculate.
3
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