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参数资料
| 型号： | PUMA68S16000XBL-012 |
| 元件分类： | SRAM |
| 英文描述： | 512K X 32 MULTI DEVICE SRAM MODULE, 12 ns, PQCC68 |
| 封装： | 25.27 X 25.27 MM, 5.08 MM HEIGHT, PLASTIC, LCC-68 |
| 文件页数： | 9/12页 |
| 文件大小： | 221K |
| 代理商： | PUMA68S16000XBL-012 |
Timing
Waveforms
Issue 5.0 November 1999
PAGE 6
Address
Data Out
Valid Data
t
RC
tAA
t
ACS
t
OLZ
t
CLZ(4,5)
t
CHZ(3,4,5)
t
OHZ
t
OH
/CS
/OE
NOTES(READ CYCLE)
1. /WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V OH or
VOL levels.
4. At any given temperature and voltage condition, t CHZ(Max.) is less than t CLZ(Min.) both for a given device and from device to
device.
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with /CS=V IL.
7. Address valid prior to coincident with /CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
9. /CS=/CS1~4
t
OE
Previous Data Valid
Data Valid
Address
Data Out
tRC
t
AA
tOH
Read Cycle 1
(Address Controlled, /CS=/OE=V
IL, /WE=VIH)
Read Cycle 2
(/WE = V
IH)
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