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参数资料
| 型号： | PUMA77S16000I-025 |
| 英文描述： | SRAM|512KX32|CMOS|QFP|68PIN|CERAMIC |
| 中文描述： | 静态存储器| 512KX32 |的CMOS | QFP封装| 68PIN |陶瓷 |
| 文件页数： | 7/10页 |
| 文件大小： | 196K |
| 代理商： | PUMA77S16000I-025 |
ISSUE 4.3 : April 2001
PUMA 2/77S16000/A - 020/025/35
6
Write Cycle No.2 Timing Waveform (5)
CS1~4
tWR(2)
t
CW
(4)
(6)
t AW
tWC
A0~A18
t
WP(1)
DW
tDH
WE1~4
D0~31out
D0~31in
WHZ(3,9)
t AS(3)
t OW
tOH
(7)
(8)
High-Z
AC Characteristics Notes
(1) A write occurs during the overlap (t
WP) of a low CS and a low WE.
(2) t
WR is measured from the earlier of CS or WE going high to the end of write cycle.
(3) During this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(4) If the CS low transition occurs simultaneously with the WE low transition or after the WE low transition, outputs remain
in a high impedance state.
(5) OE is continuously low. (OE=V
IL)
(6) D
OUT is in the same phase as written data of this write cycle.
(7) D
OUT is the read data of next address.
(8) If CS is low during this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(9) t
WHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to
output voltage levels. These parameters are sampled and not 100% tested.
Low V
CC Data Retention Timing Waveform
t R
tCDR
4.5V
2.2V
4.5V
2.2V
0V
DATA RETENTION MODE
Vcc
CS1~4
V DR
CS1~4 Vcc-0.2V
相关PDF资料 |
PDF描述 |
|---|---|
| PUMA77S16000I-35 | 15NS, 44 TQFP, IND TEMP(EPLD) |
| PUMA77S16000I-45 | 15NS, 44 PLCC, COM TEMP(EPLD) |
| PUMA77S16000I-55 | 15NS, 84 PLCC, COM TEMP(EPLD) |
| PUMA77S16000M-020 | 15NS, 68 PLCC, IND TEMP(EPLD) |
| PUMA77S16000M-025 | 15NS, 100 PQFP, IND TEMP(EPLD) |
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