参数资料
型号: PWR-82333-120S
厂商: DATA DEVICE CORP
元件分类: 运动控制电子
英文描述: BRUSHLESS DC MOTOR CONTROLLER, 50 A, DMA26
封装: 3 X 2.100 INCH, 0.390 INCH HEIGHT, PACKAGE-26
文件页数: 16/17页
文件大小: 631K
代理商: PWR-82333-120S
8
Data Device Corporation
www.ddc-web.com
PWR-82331 and PWR-82333
P-02/05-0
SHUT-DOWN INPUT (VSD)
Pin 23 (Vsd) provides a digital shut-down input, which allows the user
to completely turn-off both the upper and lower output transistors in
all 3-phases. Application of a logic “1” to the Vsd input will latch the
Digital Control/Protection circuitry thereby turning off all output tran-
sistors. The Digital Control/Protection circuitry remains latched in the
off-state and will not respond to signals on the VL or VU inputs while
the Vsd has a logic “1” applied. When the user or the sense circuitry
(as in FIGURE 9) returns the Vsd input to a logic “0,” and then the
user sets the VL and VU inputs to a logic “0” the output of the Digital
Control/Protection circuitry will clear the internal latch. When the next
rising edge (see FIGURE 10) occurs on the VL or VU digital inputs,
the output transistors will respond to the corresponding digital input.
This feature can be used with external current limit or temperature
sense circuitry to disable the drive if a fault condition occurs.
INTERNAL PROTECTION CIRCUITRY
The hybrid contains digital protection circuitry, which prevents in-
line transistors from conducting simultaneously. This, in effect,
would short circuit the power supply and would damage the out-
put stage of the hybrid. The circuitry allows only proper input sig-
nal patterns to cause output conduction. FIGURE 10 and TABLE
3 show these timing relationships. If an improper input request-
ed that the upper and lower transistors of the same phase con-
duct together, the output would be a high impedance until
removal of the illegal code from the input of the PWR-
82331/82333. A dead time of 500 ns minimum should still be
maintained between the signals at the VU and VL pins; this
ensures the complete turn off of any transistor before turning on
its associated in-line transistor.
1
0
1
0
1
0
1
0
1
0
1
0
1
0
H
Z
L
H
Z
L
H
Z
L
FIGURE 10. SHUT-DOWN (Vsd) TIMING RELATIONSHIPS
+
HCPL-5230
HCPL-5200
PWR-82331
+5V
665
2
7
5
8
7
6
5
4
1
8
6
3
8
7
4
2
3
665
0.1uF
12
Vb
16
15
9
6
2
11
7
3
8
5
1
19
22
26
SIGNAL GND
UPPER A
UPPER B
LOWER B
UPPER C
LOWER C
VSD
OVER CURRENT
LIMIT OUT
+5V
500
LF111
OP77
+15V
0.01
uF
0.01uF
-15V
R VAR
2K
25K
1K
25K
1K
2
7
4
6
3
23
24
25
20
21
18
17
VUA
VLPI
VLPO
VO A
VO B
VO C
VCC A
VCC B
VCC C
VSS A
VSS B
VSS C
GND A
GND B
GND C
VLA
VUB
VLB
VUC
VLC
VSd
0.015
5
1W
0.1uF
PHASE AOUT
(16V)
1N966A
1.6K
TIP61C
+28V
2W
PHASE BOUT
PHASE COUT
220-1,000 uF
RETURN
10W
NON-IND.
LOWER A
NOTE:
30K - (750 x Io)
0.375 x Io
R VAR =
FIGURE 9. TYPICAL OPTOCOUPLER APPLICATION
相关PDF资料
PDF描述
PWR-82333-230L BRUSHLESS DC MOTOR CONTROLLER, 50 A, DMA26
PWR-82331-120 BRUSHLESS DC MOTOR CONTROLLER, 50 A, DMA26
PWR-82331-400 BRUSHLESS DC MOTOR CONTROLLER, 50 A, DMA26
PWR-82331-410 BRUSHLESS DC MOTOR CONTROLLER, 50 A, DMA26
PWR-82333-520S BRUSHLESS DC MOTOR CONTROLLER, 50 A, DMA26
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