参数资料
型号: PWR-82333-320L
厂商: DATA DEVICE CORP
元件分类: 运动控制电子
英文描述: BRUSHLESS DC MOTOR CONTROLLER, 50 A, DMA26
文件页数: 12/17页
文件大小: 631K
代理商: PWR-82333-320L
4
Data Device Corporation
www.ddc-web.com
PWR-82331 and PWR-82333
P-02/05-0
TABLE 2. PWR-82331 AND PWR-82333 SPECIFICATIONS (CONT'D)
(TC = +25°C UNLESS OTHERWISE SPECIFIED)
PARAMETER
SYMBOL
TEST
CONDITIONS
PWR-82331
PWR-82333
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
SWITCHING CHARACTERISTICS (CONT’D)
Lower Drive:
Turn-on Propagation delay
Turn-off Propagation delay
Shut-down propagation delay (see FIG. 10)
Turn-on Rise Time
Turn-off Fall Time
td(on)
td(off)
tsd
tr
tf
Test 2
Conditions
see note 6
+5 V, Io=30 A peak
PWR-82331,
Vcc=140 V
PWR-82333, 270 V
1125
1290
1100
125
1050
1150
850
100
150
nsec
DEAD TIME
tdt
400
500
nsec
MINIMUM PULSE WIDTH
tpw
150
nsec
THERMAL
Maximum Thermal Resistance
Maximum Lead Soldering Temperature (Note 7)
Junction Temperature Range
Case Operating Temperature
Case Storage Temperature
θjc
Ts
Tj
Tco
Tcs
each transistor
-55
0.85
250
150
125
150
-55
0.85
250
150
125
150
°C/W
°C
WEIGHT
4.9
(140)
4.9
(140)
oz
(g)
Notes:
1. For Hi-Rel applications, derating per MIL-S-19500 should be observed. (Derate Vcc to 70%.)
2. Pulse width
≤ 300 ms, duty cycle ≤ 2%.
3. For PWR-82331, Vcc = 140 V, VU, VL = Logic ‘0’ and for PWR-82333, Vcc = 350 V, VU, VL = Logic ‘0.’
4. VU, VL = Logic ‘0’ on pins 17, 18, 20, 21, 24 and 25.
5. For PWR-82331, fo = 30 kHz and for PWR-82333, fo = 10 kHz.
6. Pin 16 connected to external +5 V supply.
7. Solder 1/8” from case for 5 seconds maximum.
INTRODUCTION
The 3-phase PWR-82331 and PWR-82333 are 30 A motor drive
hybrids rated at +200 V and +500 V respectively. The PWR-
82331 uses a MOSFET output stage and the PWR-82333 has
an IGBT output stage for high speed, high current, and high effi-
ciency operation. The PWR-82333 also offers high-voltage per-
formance of an IGBT for use in +270 V systems. These motor dri-
ves are ideal for use in high-performance motion control sys-
tems, servo amplifiers, and motor speed control designs.
Furthermore, multi-axis systems requiring multiple drive stages
can benefit from the small size of these power drives.
The PWR-82331/82333 can be driven directly from the commu-
tation logic, DSP, or a custom ASIC that supplies digital signals
to control the upper and lower transistors of each phase. These
highly integrated drive stages have Schmitt trigger digital inputs
FIGURE 2. INPUT/OUTPUT TIMING RELATIONSHIPS
10%
that control the high and low side of each phase. Digital protec-
tion of each phase eliminates an in-line firing condition by pre-
venting simultaneous turn-on of both the upper and lower tran-
sistors. The logic controls the high- and low-side gate drivers.
Operation from +5 to +15 V logic levels can be programmed by
applying the appropriate voltage to pin 16 (VLPI). The PWR-
82331/82333 has a ground referenced low-side gate drive. An
internal dc-dc converter supplies a floating output to each side of
the three high-side drives. This provides a continuous high-side
gate drive even during the motor stall. Pin 15 (VLPO) supplies a
+15 V output, which can be used to power the internal logic when
system usage requires +15 V logic. The high- and low-side gate
drivers control the N-channel MOSFET or IGBT output stage.
The MOSFETs used in the PWR-82331 allow output switching
up to 50 kHz, while the high-speed IGBTs in the PWR-82333 can
switch at 25 kHz. A flyback diode parallels each output transistor
and controls the regenerative energy produced by the motor.
These fast recovery diodes have faster reverse switching times
than the intrinsic body diode of the MOSFETs used in the PWR-
82331. They also protect the IGBTs used in the PWR-82333
from exceeding their emitter-to-collector breakdown voltage.
Use of a copper case and solder attachment of the output tran-
sistors achieves a low thermal resistance of 0.85° C/W maxi-
mum. Care should be taken to adequately heatsink these motor
drives to maintain a case temperature of 125°C. Junction tem-
peratures should not exceed 150°C. The PWR-82331/82333 do
not have internal short-circuit or overcurrent protection. For pro-
tection of the output transistors, these features must be added
externally to the hybrid.
(REFERENCE TABLE 2. ALSO.)
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