参数资料
型号: PWR-82341-150Q
厂商: DATA DEVICE CORP
元件分类: 运动控制电子
英文描述: BRUSHLESS DC MOTOR CONTROLLER, 10 A, DIP34
封装: 1.800 X 1.400 INCH, 0.250 INCH HEIGHT, PACKAGE-34
文件页数: 5/9页
文件大小: 280K
代理商: PWR-82341-150Q
4
1
2
V
v
VO
V
H
vp
N
CHARGE PUMP
DIGITAL
CONTROL
AND
PROTECTION
CIRCUITRY
MOTOR
VCC
VOA
VSS
VCC
V
OB
V
SS
+ 28 V
TANT
+
PWR-82341
DRIVE
A
DRIVE
B
+ 15 V
POSITION
COMMAND
POSITION
LOOP
AND
PWM
+ +CAP
-CAP
V+
GND
V
UA
V
UB
V
LB
V
Sd
VLPI
V
LA
FIGURE 3. HYSTERESIS DEFINITION AND CHARACTERISTICS
FIGURE 4. TYPICAL INTERFACE WITH A MOTOR AND PWM
that the upper and lower transistors of the same phase conduct
together, the output would be a high impedance until removal of
the illegal code from the input of the PWR-82341. A dead time
of 400 nsec minimum should still be maintained between
the signals at the Vu and VL pins; this ensures the complete
turn-off of any transistor before turning on its associated in-line
transistor.
SHUT-DOWN INPUT (VSd)
The VSd pin provides a digital shut-down input, which allows the
user to completely turn off both the upper and lower-output tran-
sistors in all three phases. Application of a logic “1” to the VSd
input will latch the Digital Control/Protection circuitry thereby
turning off all output transistors. The Digital Control/Protection
circuitry remains latched in the off state and will not respond to
signals on the VL or VU inputs while the VSd has a logic “1”
applied. When the user or the sense circuitry (as in FIGURE 6)
returns the VSd input to a logic “0”, and then the user sets the VL
and VU inputs to a logic “0” the output of the Digital
Control/Protection circuitry will clear the internal latch. When the
next rising edge (see FIGURE 5) occurs on the VL or VU digital
inputs, the outputs transistors will respond to the corresponding
digital input. This feature can be used with external current limit
or temperature sense circuitry to disable the drive if a fault con-
dition occurs (see FIGURE 6).
INTERNAL PROTECTION CIRCUITRY
The hybrid contains digital protection circuitry, which prevents in-
line transistors from conducting simultaneously. This, in effect,
would short circuit the power supply and would damage the out-
put stage of the hybrid. This circuit permits only proper input sig-
nal patterns to produce output conduction. TABLE 3 lists the
input/output timing relationships. If an improper input requested
TABLE 3. INPUT-OUTPUT TRUTH TABLE
INPUTS
OUTPUTS
UPPERS
LOWERS
CONTROL
V
UA
V
UB
V
LA
V
LB
V
SD
V
OA
V
OB
00
11
0
L
01
10
0
L
H
11
00
0
H
1X
0
Z
X
X1
0
X
Z
00
0
z
xx
1
z
H = High Level
L = Low Level
X = Don’t Care
Z = High Impedance State (off)
相关PDF资料
PDF描述
PWR-82341-130S BRUSHLESS DC MOTOR CONTROLLER, 10 A, DIP34
PWR-82341-110L BRUSHLESS DC MOTOR CONTROLLER, 10 A, DIP34
PWR-82341-110Q BRUSHLESS DC MOTOR CONTROLLER, 10 A, DIP34
PWR-82341-150S BRUSHLESS DC MOTOR CONTROLLER, 10 A, DIP34
PWR-82341-150 BRUSHLESS DC MOTOR CONTROLLER, 10 A, DIP34
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