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参数资料
| 型号： | PZ3064I12BC |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | PLD |
| 英文描述： | 64 macrocell CPLD |
| 中文描述： | EE PLD, 14.5 ns, PQFP44 |
| 封装： | 10 X 10 X 1 MM, PLASTIC, SOT-376-1, TQFP-44 |
| 文件页数： | 6/20页 |
| 文件大小： | 245K |
| 代理商： | PZ3064I12BC |
Philips Semiconductors
Product specification
PZ3064
64 macrocell CPLD
1997 Mar 05
86
Simple Timing Model
Figure 4 shows the CoolRunner
Timing Model. The CoolRunner
timing model looks very much like a 22V10 timing model in that
there are three main timing parameters, including t
PD
, t
SU
, and t
CO
.
In other competing architectures, the user may be able to fit the
design into the CPLD, but is not sure whether system timing
requirements can be met until after the design has been fit into the
device. This is because the timing models of competing
architectures are very complex and include such things as timing
dependencies on the number of parallel expanders borrowed,
sharable expanders, varying number of X and Y routing channels
used, etc. In the XPLA
architecture, the user knows up front
whether the design will meet system timing requirements. This is
due to the simplicity of the timing model. For example, in the
PZ3064 device, the user knows up front that if a given output uses
5 product terms or less, the t
PD
= 10ns, the t
SU_PAL
= 6ns, and the
t
CO
= 7ns. If an output is using 6 to 37 product terms, an additional
2ns must be added to the t
PD
and t
SU
timing parameters to account
for the time to propagate through the PLA array.
TotalCMOS
Design Technique
for Fast Zero Power
Philips is the first to offer a TotalCMOS
CPLD, both in process
technology and design technique. Philips employs a cascade of
CMOS gates to implement its Sum of Products instead of the
traditional sense amp approach. This CMOS gate implementation
allows Philips to offer CPLDs which are both high performance and
low power, breaking the paradigm that to have low power, you must
have low performance. Refer to Figure 5 and Table 2 showing the I
DD
vs. Frequency of our PZ3064 TotalCMOS
CPLD.
OUTPUT PIN
INPUT PIN
SP00441
t
PD_PAL
= COMBINATORIAL PAL ONLY
t
PD_PLA
= COMBINATORIAL PAL + PLA
CLOCK
OUTPUT PIN
INPUT PIN
D
Q
REGISTERED
t
SU_PAL
= PAL ONLY
t
SU_PLA
= PAL + PLA
REGISTERED
t
CO
Figure 4.
CoolRunner
Timing Model
TYPICAL
I
(mA)
FREQUENCY (MHz)
SP00460A
0
20
40
60
80
100
0
20
40
60
80
100
Figure 5.
I
DD
vs. Frequency @ V
DD
= 3.3V, 25
°
C
Table 2. I
DD
vs. Frequency
V
DD
= 3.3V
FREQUENCY (MHz)
0
20
40
60
80
100
Typical I
DD
( mA)
0.04
13
26
40
50
63
相关PDF资料 |
PDF描述 |
|---|---|
| PZ3064I15A44 | 64 macrocell CPLD |
| PZ3064 | 64 macrocell CPLD |
| PZ3064-10A68 | Circular Connector; Body Material:Aluminum; Series:PT06; No. of Contacts:3; Connector Shell Size:12; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Circular Contact Gender:Socket; Insert Arrangement:12-3 |
| PZ3064-10A84 | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT06; No. of Contacts:3; Connector Shell Size:12; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Body Style:Straight |
| PZ3064-10BB1 | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT06; No. of Contacts:3; Connector Shell Size:12; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Body Style:Straight |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PZ3064I12BC-S | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Electrically-Erasable Complex PLD |
| PZ3064I15A44 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:64 macrocell CPLD |
| PZ3064I15A68 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:64 macrocell CPLD |
| PZ3064I15A84 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:64 macrocell CPLD |
| PZ3064I15BB | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Electrically-Erasable Complex PLD |
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