- 您现在的位置：买卖IC网 > PDF目录368398 > PZ3064I15A84 (NXP SEMICONDUCTORS) 64 macrocell CPLD PDF资料下载
参数资料
| 型号： | PZ3064I15A84 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | PLD |
| 英文描述： | 64 macrocell CPLD |
| 中文描述： | EE PLD, 17.5 ns, PQCC84 |
| 封装： | PEDESTAL, PLASTIC, SOT-189-3, LCC-84 |
| 文件页数： | 8/20页 |
| 文件大小： | 245K |
| 代理商： | PZ3064I15A84 |
Philips Semiconductors
Product specification
PZ3064
64 macrocell CPLD
1997 Mar 05
88
DC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES
Commercial: 0
°
C
≤
T
amb
≤
+70
°
C; 3.0V
≤
V
DD
≤
3.6V
SYMBOL
PARAMETER
V
IL
Input voltage low
V
IH
Input voltage high
V
I
Input clamp voltage
V
OL
Output voltage low
V
OH
Output voltage high
I
I
Input leakage current
I
OZ
3-Stated output leakage current
I
DDQ
Standby current
TEST CONDITIONS
V
DD
= 3.0V
V
DD
= 3.6V
V
DD
= 3.0V, I
IN
= –18mA
V
DD
= 3.0V, I
OL
= 8mA
V
DD
= 3.0V, I
OH
= –8mA
V
IN
= 0 to V
DD
V
IN
= 0 to V
DD
V
DD
= 3.6V, T
amb
= 0
°
C
V
DD
= 3.6V, T
amb
= 0
°
C @ 1MHz
V
DD
= 3.6V, T
amb
= 0
°
C @ 50MHz
1 pin at a time for no longer than 1 second
T
amb
= 25
°
C, f = 1MHz
T
amb
= 25
°
C, f = 1MHz
T
amb
= 25
°
C, f = 1MHz
MIN.
MAX.
0.8
UNIT
V
V
V
V
V
μ
A
μ
A
μ
A
mA
2.0
–1.2
0.5
2.4
–10
–10
10
10
50
1
I
DDD1
Dynamic current
40
mA
I
OS
C
IN
C
CLK
C
I/O
Short circuit output current
Input pin capacitance
Clock input capacitance
I/O pin capacitance
–5
–100
8
12
10
mA
pF
pF
pF
5
NOTE:
1. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs enabled and unloaded.
Inputs are tied to V
DD
or ground. This parameter guaranteed by design and characterization, not testing.
AC ELECTRICAL CHARACTERISTICS
1
FOR COMMERCIAL GRADE DEVICES
Commercial: 0
°
C
≤
T
amb
≤
+70
°
C; 3.0V
≤
V
DD
≤
3.6V
SYMBOL
PARAMETER
–10
–12
UNIT
MIN.
2
3
2
5.5
8
MAX.
10
12.5
7
MIN.
2
3
2
7
9.5
MAX.
12
14.5
8
t
PD_PAL
t
PD_PLA
t
CO
t
SU_PAL
t
SU_PLA
t
H
t
CH
t
CL
t
R
t
F
f
MAX1
f
MAX2
f
MAX3
t
BUF
t
PDF_PAL
t
PDF_PLA
t
CF
t
INIT
t
ER
t
EA
t
RP
t
RR
NOTES:
1. Specifications measured with one output switching. See Figure 6 and Table 3 for derating.
2. This parameter guaranteed by design and characterization, not by test.
3. Output C
L
= 5pF.
Propagation delay time, input (or feedback node) to output through PAL
Propagation delay time, input (or feedback node) to output through PAL & PLA
Clock to out delay time
Setup time (from input or feedback node) through PAL
Setup time (from input or feedback node) through PAL + PLA
Hold time
Clock High time
Clock Low time
Input Rise time
Input Fall time
Maximum FF toggle rate
2
(1/t
CH
+ t
CL
)
Maximum internal frequency
2
(1/t
SUPAL
+ t
CF
)
Maximum external frequency
2
(1/t
SUPAL
+ t
CO
)
Output buffer delay time
Input (or feedback node) to internal feedback node delay time through PAL
Input (or feedback node) to internal feedback node delay time through PAL+PLA
Clock to internal feedback node delay time
Delay from valid V
DD
to valid reset
Input to output disable
3
Input to output valid
Input to register preset
Input to register reset
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
μ
s
ns
ns
ns
ns
0
0
4
4
5
5
20
20
20
20
125
91
80
100
74
67
1.5
8.5
11
5.5
50
12.5
12.5
15
15
1.5
10.5
13
6.5
50
14
14
16
16
相关PDF资料 |
PDF描述 |
|---|---|
| PZ3064I15BB1 | 64 macrocell CPLD |
| PZ3064I15BC | 64 macrocell CPLD |
| PZ3064I12A68 | DIODE ZENER 150MW 6.2V 0603 |
| PZ3064I12A44 | 64 macrocell CPLD |
| PZ3064I12A84 | 64 macrocell CPLD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PZ3064I15BB | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Electrically-Erasable Complex PLD |
| PZ3064I15BB1 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:64 macrocell CPLD |
| PZ3064I-15BB1 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Electrically-Erasable Complex PLD |
| PZ3064I15BC | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:64 macrocell CPLD |
| PZ3064I15BC-S | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Electrically-Erasable Complex PLD |
发布紧急采购，3分钟左右您将得到回复。