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参数资料
| 型号： | PZ5032CS7BC |
| 英文描述： | Electrically-Erasable Complex PLD |
| 中文描述： | 电可擦除复杂可编程逻辑器件 |
| 文件页数： | 6/14页 |
| 文件大小： | 107K |
| 代理商： | PZ5032CS7BC |
Philips Semiconductors
Product specification
PZ5032
32 macrocell CPLD
1997 Feb 20
6
Simple Timing Model
Figure 4 shows the CoolRunner
Timing Model. The CoolRunner
timing model looks very much like a 22V10 timing model in that
there are three main timing parameters, including t
PD
, t
SU
, and t
CO
.
In other competing architectures, the user may be able to fit the
design into the CPLD, but is not sure whether system timing
requirements can be met until after the design has been fit into the
device. This is because the timing models of competing
architectures are very complex and include such things as timing
dependencies on the number of parallel expanders borrowed,
sharable expanders, varying number of X and Y routing channels
used, etc. In the XPLA
architecture, the user knows up front
whether the design will meet system timing requirements. This is
due to the simplicity of the timing model. For example, in the
PZ5032 device, the user knows up front that if a given output uses 5
product terms or less, the t
PD
= 6ns, the t
SU
= 4.5ns, and the
t
CO
= 5ns. If an output is using 6 to 37 product terms, an additional
2ns must be added to the t
PD
and t
SU
timing parameters to account
for the time to propagate through the PLA array.
TotalCMOS
Design Technique
for Fast Zero Power
Philips is the first to offer a TotalCMOS
CPLD, both in process
technology and design technique. Philips employs a cascade of
CMOS gates to implement its Sum of Products instead of the
traditional sense amp approach. This CMOS gate implementation
allows Philips to offer CPLDs which are both high performance and
low power, breaking the paradigm that to have low power, you must
have low performance. Refer to Figure 5 and Table 2 showing the I
DD
vs. Frequency of our PZ5032 TotalCMOS
CPLD.
OUTPUT PIN
INPUT PIN
SP00441
t
PD_PAL
= COMBINATORIAL PAL ONLY
t
PD_PLA
= COMBINATORIAL PAL + PLA
CLOCK
OUTPUT PIN
INPUT PIN
D
Q
REGISTERED
t
SU_PAL
= PAL ONLY
t
SU_PLA
= PAL + PLA
REGISTERED
t
CO
Figure 4.
CoolRunner
Timing Model
TYPICAL
I
(mA)
FREQUENCY (MHz)
SP00442
Figure 5.
I
DD
vs. Frequency @ V
DD
= 5.0V, 25
°
C
Table 2. I
DD
vs Frequency
V
DD
= 5.00V
FREQ
(MHz)
0
20
40
60
80
100
120
140
160
180
Typical
I
DD
( mA)
0.05
9.62
17.5
25.6
32.5
40.8
49.0
55.9
64.2
75.2
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