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参数资料
| 型号： | PZ5032I10BC |
| 英文描述： | Electrically-Erasable Complex PLD |
| 中文描述： | 电可擦除复杂可编程逻辑器件 |
| 文件页数： | 3/14页 |
| 文件大小： | 107K |
| 代理商： | PZ5032I10BC |
Philips Semiconductors
Product specification
PZ5032
32 macrocell CPLD
1997 Feb 20
3
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
DESCRIPTION
DRAWING NUMBER
PZ5032–6A44
44-pin PLCC, 6ns t
PD
Commercial temp range, 5 volt power supply,
±
5%
SOT187-2
PZ5032–7A44
44-pin PLCC, 7.5ns t
PD
Commercial temp range, 5 volt power supply,
±
5%
SOT187-2
PZ5032–10A44
44-pin PLCC, 10ns t
PD
Commercial temp range, 5 volt power supply,
±
5%
SOT187-2
PZ5032I7A44
44-pin PLCC, 7.5ns t
PD
Industrial temp range, 5 volt power supply,
±
10%
SOT187-2
PZ5032I10A44
44-pin PLCC, 10ns t
PD
Industrial temp range, 5 volt power supply,
±
10%
SOT187-2
PZ5032–6BC
44-pin TQFP, 6ns t
PD
,
Commercial temp range, 5 volt power supply,
±
5%
SOT376-1
PZ5032–7BC
44-pin TQFP, 7.5ns t
PD
Commercial temp range, 5 volt power supply,
±
5%
SOT376-1
PZ5032–10BC
44-pin TQFP, 10ns t
PD
Commercial temp range, 5 volt power supply,
±
5%
SOT376-1
PZ5032I7BC
44-pin TQFP, 7.5ns t
PD
Industrial temp range, 5 volt power supply,
±
10%
SOT376-1
PZ5032I10BC
44-pin TQFP, 10ns t
PD
Industrial temp range, 5 volt power supply,
±
10%
SOT376-1
XPLA
ARCHITECTURE
Figure 1 shows a high level block diagram of a 64 macrocell device
implementing the XPLA
architecture. The XPLA
architecture
consists of logic blocks that are interconnected by a Zero-power
Interconnect Array (ZIA). The ZIA is a virtual crosspoint switch. Each
logic block is essentially a 36V16 device with 36 inputs from the ZIA
and 16 macrocells. Each logic block also provides 32 ZIA feedback
paths from the macrocells and I/O pins.
From this point of view, this architecture looks like many other CPLD
architectures. What makes the CoolRunner
family unique is what
is inside each logic block and the design technique used to
implement these logic blocks. The contents of the logic block will be
described next.
Logic Block Architecture
Figure 2 illustrates the logic block architecture. Each logic block
contains control terms, a PAL array, a PLA array, and 16 macrocells.
the 6 control terms can individually be configured as either SUM or
PRODUCT terms, and are used to control the preset/reset and
output enables of the 16 macrocells’ flip-flops. The PAL array
consists of a programmable AND array with a fixed OR array, while
the PLA array consists of a programmable AND array with a
programmable OR array. The PAL array provides a high speed path
through the array, while the PLA array provides increased product
term density.
Each macrocell has 5 dedicated product terms from the PAL array.
The pin-to-pin t
PD
of the PZ5032 device through the PAL array is
6ns. This performance is equivalent to the fastest 5 volt CPLD
available today. If a macrocell needs more than 5 product terms, it
simply gets the additional product terms from the PLA array. The
PLA array consists of 32 product terms, which are available for use
by all 16 macrocells. The additional propagation delay incurred by a
macrocell using 1 or all 32 PLA product terms is just 2ns. So the
total pin-to-pin t
PD
for the PZ5032 using 6 to 37 product terms is 8ns
(6ns for the PAL + 2ns for the PLA).
LOGIC
BLOCK
I/O
36
16
16
36
16
16
MC0
MC1
MC15
I/O
MC0
MC1
MC15
LOGIC
BLOCK
I/O
36
16
16
36
16
16
MC0
MC1
MC15
I/O
MC0
MC1
MC15
SP00439
ZIA
LOGIC
BLOCK
LOGIC
BLOCK
Figure 1.
Philips XPLA CPLD Architecture
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