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参数资料
| 型号： | PZ5128IS10BB1 |
| 英文描述： | Electrically-Erasable Complex PLD |
| 中文描述： | 电可擦除复杂可编程逻辑器件 |
| 文件页数： | 16/22页 |
| 文件大小： | 180K |
| 代理商： | PZ5128IS10BB1 |
Philips Semiconductors
Product specification
PZ5128
128 macrocell CPLD
1997 Aug 12
16
160-Pin Plastic Quad Flat Package
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
Function
NC
NC
NC
NC
NC
NC
NC
V
I/O-B15 (TDI)
I/O-B13
I/O-B12
I/O-B11
I/O-B10
I/O-B8
I/O-B7
I/O-B5
GND
I/O-B4
I/O-B3
I/O-B2
I/O-B0
I/O-C15 (TMS)
I/O-C13
I/O-C12
I/O-C11
V
DD
I/O-C10
I/O-C8
I/O-C7
I/O-C5
I/O-C4
I/O-C3
I/O-C2
NC
NC
NC
NC
NC
NC
NC
I/O-C0
GND
I/O-D15
NC
NC
NC
NC
I/O-D13
I/O-D12
I/O-D11
I/O-D10
I/O-D8
I/O-D7
Pin
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
Function
I/O-D5
V
I/O-D4
I/O-D3
I/O-D2
I/O-D0/CLK2
GND
V
I/O-E0/CLK1
I/O-E2
I/O-E3
I/O-E4
GND
I/O-E5
I/O-E7
I/O-E8
I/O-E10
I/O-E11
I/O-E12
I/O-E13
NC
NC
NC
NC
I/O-E15
V
DD
I/O-F0
NC
NC
NC
NC
NC
NC
NC
I/O-F2
I/O-F3
I/O-F4
I/O-F5
I/O-F7
I/O-F8
I/O-F10
GND
I/O-F11
I/O-F12
I/O-F13
I/O-F15 (TCK)
I/O-G0
I/O-G2
I/O-G3
I/O-G4
V
DD
I/O-G5
I/O-G7
Pin
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
Function
I/O-G8
I/O-G10
I/O-G11
I/O-G12
I/O-G13
I/O-G15 (TDO)
GND
NC
NC
NC
NC
NC
NC
NC
I/O-H0
I/O-H2
I/O-H3
NC
NC
NC
NC
I/O-H4
I/O-H5
I/O-H7
I/O-H8
I/O-H10
V
I/O-H11
I/O-H12
I/O-H13
I/O-H15
GND
IN0/CLK0
IN2-gtsn
IN1
IN3
V
I/O-A15/CLK3
I/O-A13
I/O-A12
I/O-A11
GND
I/O-A10
I/O-A8
I/O-A7
I/O-A5
I/O-A4
NC
NC
NC
NC
I/O-A3
I/O-A2
I/O-A0
*
THE TEST MODE SELECT (TMS) FUNCTION IS
INACTIVE ON NON-ISR ARCHITECTURES.
SP00470A
PQFP
160
1
40
41
81
80
121
120
Package Thermal Characteristics
Philips Semiconductors uses the Temperature Sensitive Parameter
(TSP) method to test thermal resistance. This method meets
Mil-Std-883C Method 1012.1 and is described in Philips 1995 IC
Package Databook Thermal resistance varies slightly as a function
of input power. As input power increases, thermal resistance
changes approximately 5% for a 100% change in power.
Figure 7 is a derating curve for the change in
Θ
JA
with airflow based
on wind tunnel measurements. It should be noted that the wind flow
dynamics are more complex and turbulent in actual applications
than in a wind tunnel. Also, the test boards used in the wind tunnel
contribute significantly to forced convection heat transfer, and may
not be similar to the actual circuit board, especially in size.
Package
Θ
JA
84-pin PLCC
32.8
°
C/W
100-pin PQFP
41.2
°
C/W
100-pin TQFP
47.4
°
C/W
128-pin LQFP
45.0
°
C/W
160-pin PQFP
31.4
°
C/W
0
10
20
30
40
50
0
1
2
3
4
5
PERCENTAGE
REDUCTION IN
JA
(%)
AIR FLOW (m/s)
PLCC/
QFP
SP00419A
Figure 7.
Average Effect of Airflow on
Θ
JA
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