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| 型号： | PZ5128IS10BP-S |
| 英文描述： | Electrically-Erasable Complex PLD |
| 中文描述： | 电可擦除复杂可编程逻辑器件 |
| 文件页数： | 2/22页 |
| 文件大小： | 180K |
| 代理商： | PZ5128IS10BP-S |
Philips Semiconductors
Product specification
PZ5128
128 macrocell CPLD
2
1997 Aug 12
853–2023 18271
FEATURES
Industry’s first TotalCMOS
PLD – both CMOS design and
process technologies
Fast Zero Power (FZP
) design technique provides ultra-low
power and very high speed
IEEE 1149.1–compliant, JTAG Testing Capability
–
4 pin JTAG interface (TCK, TMS, TDI, TDO)
–
IEEE 1149.1 TAP Controller
–
JTAG commands include: Bypass, Sample/Preload, Extest,
Usercode, Idcode, HighZ
5 Volt, In–System Programmable (ISP) using the JTAG interface
–
On–chip supervoltage generation
–
ISP commands include: Enable, Erase, Program, Verify
–
Supported by multiple ISP programming platforms
High speed pin-to-pin delays of 7.5ns
Ultra-low static power of less than 100
μ
A
Dynamic power that is 70% lower at 50MHz than competing
devices
100% routable with 100% utilization while all pins and all
macrocells are fixed
Deterministic timing model that is extremely simple to use
4 clocks with programmable polarity at every macrocell
Support for complex asynchronous clocking
Innovative XPLA
architecture combines high speed with
extreme flexibility
1000 erase/program cycles guaranteed
20 years data retention guaranteed
Logic expandable to 37 product terms
PCI compliant
Advanced 0.5
μ
E
2
CMOS process
Security bit prevents unauthorized access
Design entry and verification using industry standard and Philips
CAE tools
Reprogrammable using industry standard device programmers
Innovative Control Term structure provides either sum terms or
product terms in each logic block for:
–
Programmable 3-State buffer
–
Asynchronous macrocell register preset/reset
Programmable global 3-State pin facilitates ‘bed of nails’ testing
without using logic resources
Available in PLCC, TQFP, and PQFP packages
Available in both Commercial and Industrial grades
Table 1. PZ5128 Features
PZ5128
4000
100
96
128
7.5
Usable gates
Maximum inputs
Maximum I/Os
Number of macrocells
Propagation delay (ns)
Packages
84-pin PLCC, 100-pin PQFP,
100-pin TQFP 128-pin LQFP,
160-pin PQFP
DESCRIPTION
The PZ5128 CPLD (Complex Programmable Logic Device) is the
third in a family of Fast Zero Power (FZP
) CPLDs from Philips
Semiconductors. These devices combine high speed and zero
power in a 128 macrocell CPLD. With the FZP
design technique,
the PZ5128 offers true pin-to-pin speeds of 7.5ns, while
simultaneously delivering power that is less than 100
μ
A at standby
without the need for ‘turbo bits’ or other power down schemes. By
replacing conventional sense amplifier methods for implementing
product terms (a technique that has been used in PLDs since the
bipolar era) with a cascaded chain of pure CMOS gates, the
dynamic power is also substantially lower than any competing CPLD
– 70% lower at 50MHz. These devices are the first TotalCMOS
PLDs, as they use both a CMOS process technology
and
the
patented full CMOS FZP
design technique. For 3V applications,
Philips also offers the high speed PZ3128 CPLD that offers these
features in a full 3V implementation.
The Philips FZP
CPLDs introduce the new patent-pending XPLA
(eXtended Programmable Logic Array) architecture. The XPLA
architecture combines the best features of both PLA and PAL
type
structures to deliver high speed and flexible logic allocation that
results in superior ability to make design changes with fixed pinouts.
The XPLA
structure in each logic block provides a fast 10ns PAL
path with 5 dedicated product terms per output. This PAL
path is
joined by an additional PLA structure that deploys a pool of 32
product terms to a fully programmable OR array that can allocate
the PLA product terms to any output in the logic block. This
combination allows logic to be allocated efficiently throughout the
logic block and supports as many as 37 product terms on an output.
The speed with which logic is allocated from the PLA array to an
output is only 2ns, regardless of the number of PLA product terms
used, which results in worst case t
PD
’s of only 9.5ns from any pin to
any other pin. In addition, logic that is common to multiple outputs
can be placed on a single PLA product term and shared across
multiple outputs via the OR array, effectively increasing design
density.
The PZ5128 CPLDs are supported by industry standard CAE tools
(Cadence, Mentor, Synopsys, Synario, Viewlogic, MINC), using text
(Abel, VHDL, Verilog) and/or schematic entry. Design verification
uses industry standard simulators for functional and timing
simulation. Development is supported on personal computer, Sparc,
and HP platforms. Device fitting uses either MINC or Philips
Semiconductors-developed tools.
The PZ5128 CPLD is electrically reprogrammable using industry
standard device programmers from vendors such as Data I/O, BP
Microsystems, SMS, and others. The PZ5128 also includes an
industry-standard, IEEE 1149.1, JTAG interface through which
in-system programming (ISP) and reprogramming of the device is
supported.
PAL is a registered trademark of Advanced Micro Devices, Inc.
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