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| 型号： | PZ5128IS15A84 |
| 英文描述： | Electrically-Erasable Complex PLD |
| 中文描述： | 电可擦除复杂可编程逻辑器件 |
| 文件页数： | 9/22页 |
| 文件大小： | 180K |
| 代理商： | PZ5128IS15A84 |
Philips Semiconductors
Product specification
PZ5128
128 macrocell CPLD
1997 Aug 12
9
Table 5. PZ5128 Low-Level JTAG Boundary-Scan Commands
INSTRUCTION
(Instruction Code)
Register Used
DESCRIPTION
Sample/Preload
(0010)
Boundary–Scan Register
The mandatory SAMPLE/PRELOAD instruction allows a snapshot of the normal operation of the component
to be taken and examined. It also allows data values to be loaded onto the latched parallel outputs of the
Boundary-Scan Shift-Register prior to selection of the other boundary-scan test instructions.
Extest
(0000)
Boundary-Scan Register
The mandatory EXTEST instruction allows testing of off-chip circuitry and board level interconnections. Data
would typically be loaded onto the latched parallel outputs of Boundary-Scan Shift-Register using the
Sample/Preload instruction prior to selection of the EXTEST instruction.
Bypass
(1111)
Bypass Register
Places the 1 bit bypass register between the TDI and TDO pins, which allows the BST data to pass
synchronously through the selected device to adjacent devices during normal device operation. The Bypass
instruction can be entered by holding TDI at a constant high value and completing an Instruction-Scan cycle.
Idcode
(0001)
Boundary-Scan Register
Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE to be serially shifted
out of TDO. The IDCODE instruction permits blind interrogation of the components assembled onto a printed
circuit board. Thus, in circumstances where the component population may vary, it is possible to determine
what components exist in a product.
HighZ
(0101)
Bypass Register
The HIGHZ instruction places the component in a state in which all of its system logic outputs are placed in
an inactive drive state (e.g., high impedance). In this state, an in-circuit test system may drive signals onto
the connections normally driven by a component output without incurring the risk of damage to the
component. The HighZ instruction also forces the Bypass Register between TDI and TDO.
5-Volt, In-System Programming (ISP)
ISP is the ability to reconfigure the logic and functionality of a
device, printed circuit board, or complete electronic system before,
during, and after its manufacture and shipment to the end customer.
ISP provides substantial benefits in each of the following areas:
Design
–
Faster time-to-market
–
Debug partitioning and simplified prototyping
–
Printed circuit board reconfiguration during debug
–
Better device and board level testing
Manufacturing
–
Multi-Functional hardware
–
Reconfiguarability for Test
–
Eliminates handling of “fine lead-pitch” components for
programming
–
Reduced Inventory and manufacturing costs
–
Improved quality and reliability
Field Support
–
Easy remote upgrades and repair
–
Support for field configuration, re-configuration, and
customization
The Philips PZ5128 allows for 5-Volt, in-system
programming/reprogramming of its EEPROM cells via its JTAG
interface. An on-chip charge pump eliminates the need for
externally-provided supervoltages, so that the PZ5128 may be
easily programmed on the circuit board using only the 5-volt supply
required by the device for normal operation. A set of low-level ISP
basic commands implemented in the PZ5128 enable this feature.
The ISP commands implemented in the Philips PZ5128 are
specified in Table 6. Please note that an ENABLE command must
precede all ISP commands
unless
an ENABLE command has
already been given for a preceding ISP command
and
the device
has not gone through a Test-Logic/Rest TAP Controller State.
Table 6. Low Level ISP Commands
INSTRUCTION
(Register Used)
INSTRUCTION
CODE
DESCRIPTION
Enable
(ISP Shift Register)
1001
Enables the Erase, Program, and Verify commands. Using the ENABLE instruction before the
Erase, Program, and Verify instructions allows the user to specify the outputs the device using
the JTAG Boundary–Scan SAMPLE/PRELOAD command.
Erase
(ISP Shift Register)
1010
Erases the entire EEPROM array. The outputs during this operation can be defined by user by
using the JTAG SAMPLE/PRELOAD command.
Program
(ISP Shift Register)
1011
Programs the data in the ISP Shift Register into the addressed EEPROM row. The outputs
during this operation can be defined by user by using the JTAG SAMPLE/PRELOAD command.
Verify
(ISP Shift Register)
1100
Transfers the data from the addressed row to the ISP Shift Register. The data can then be
shifted out and compared with the JEDEC file. The outputs during this operation can be defined
by user by using the JTAG SAMPLE/PRELOAD command.
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