- 您现在的位置：买卖IC网 > PDF目录134952 > Q80C32E-42:D (ATMEL CORP) 8-BIT, 42 MHz, MICROCONTROLLER, CQFP44 PDF资料下载
参数资料
| 型号： | Q80C32E-42:D |
| 厂商： | ATMEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, 42 MHz, MICROCONTROLLER, CQFP44 |
| 封装： | CERAMIC, QFP-44 |
| 文件页数： | 38/46页 |
| 文件大小： | 7004K |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页当前第38页第39页第40页第41页第42页第43页第44页第45页第46页
666
32117D–AVR-01/12
AT32UC3C
to an interrupt, and thus might lead to difficulties for interfacing with some serial peripherals
requiring the chip select line to remain active during a full set of transfers.
To facilitate interfacing with such devices, the CSRn registers can be configured with the Chip
Select Active After Transfer bit written to one (CSRn.CSAAT) . This allows the chip select lines
to remain in their current state (low = active) until transfer to another peripheral is required.
When the CSRn.CSAAT bit is written to qero, the NPCS does not rise in all cases between two
transfers on the same peripheral. During a transfer on a Chip Select, the SR.TDRE bit rises as
soon as the content of the TDR is transferred into the internal shifter. When this bit is detected
the TDR can be reloaded. If this reload occurs before the end of the current transfer and if the
next transfer is performed on the same chip select as the current transfer, the Chip Select is not
de-asserted between the two transfers. This might lead to difficulties for interfacing with some
serial peripherals requiring the chip select to be de-asserted after each transfer. To facilitate
interfacing with such devices, the CSRn registers can be configured with the Chip Select Not
Active After Transfer bit (CSRn.CSNAAT) written to one. This allows to de-assert systematically
the chip select lines during a time DLYBCS. (The value of the CSRn.CSNAAT bit is taken into
account only if the CSRn.CSAAT bit is written to zero for the same Chip Select).
Figure 26-8 on page 667 shows different peripheral deselection cases and the effect of the
CSRn.CSAAT and CSRn.CSNAAT bits.
26.7.3.8
FIFO management
A FIFO has been implemented in Reception FIFO (both in master and in slave mode), in order to
be able to store up to 4 characters without causing an overrun error. If an attempt is made to
store a fifth character, an overrun error rises. If such an event occurs, the FIFO must be flushed.
There are two ways to Flush the FIFO:
By performing four read accesses of the RDR (the data read must be ignored)
By writing a one to the Flush Fifo Command bit in the CR register (CR.FLUSHFIFO).
After that, the SPI is able to receive new data.
相关PDF资料 |
PDF描述 |
|---|---|
| Q80C32E-42SHXXX:RD | 8-BIT, 42 MHz, MICROCONTROLLER, CQFP44 |
| Q80C32E-L16:RD | 8-BIT, 16 MHz, MICROCONTROLLER, CQFP44 |
| Q80C32E-L16:R | 8-BIT, 16 MHz, MICROCONTROLLER, CQFP44 |
| QS5LV931-80Q | 5LV SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| QS5917T-100TJ | 5917 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| Q80N-5 | 制造商:POWERBOX 制造商全称:Powerbox 功能描述:0.5 WATTS - 100 - 10KV SINGLE OUTPUT DC/DC INDUSTRIAL |
| Q-810 | 功能描述:交流电源插头和插座 NEMA L5-15P LOCKING DEVICE RoHS:否 制造商:Hirose Connector 产品:Plugs 系列: 电流额定值:3 A 电压额定值:30 V 安装角:Straight 安装风格:Cable 颜色: 端口数量: |
| Q81022511000000 | 制造商:Epson Electronics America Inc 功能描述:TF2-J4DB1 184.3200MHZ |
| Q811 | 制造商:Captive Fastener Corporation 功能描述: |
| Q-812 | 制造商:Qualtek Electronics Corporation 功能描述:NEMA TWIST-LOCK 制造商:Qualtek Electronics Corporation 功能描述:Nema St Blade Twist Lock |
发布紧急采购，3分钟左右您将得到回复。