参数资料
型号: Q80C52XXX-12SHXXX:D
厂商: ATMEL CORP
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQFP44
封装: CERAMIC, QFP-44
文件页数: 14/134页
文件大小: 3805K
110
8011Q–AVR–02/2013
ATmega164P/324P/644P
Bit 2 – OCF0B: Timer/Counter 0 Output Compare B Match Flag
The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in
OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware when executing the cor-
responding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to
the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable),
and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed.
Bit 1 – OCF0A: Timer/Counter 0 Output Compare A Match Flag
The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data
in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing the cor-
responding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to
the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable),
and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed.
Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by
writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt
Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed.
The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Table 12-8, ”Waveform
相关PDF资料
PDF描述
Q80C52XXX-12SHXXX:R 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQFP44
Q80C52XXX-16SHXXX:D 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQFP44
Q80C52XXX-20:RD 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQFP44
Q80C52XXX-20SHXXX:D 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQFP44
Q80C52XXX-25:R 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQFP44
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