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参数资料
| 型号： | QL2009-XPQ208C |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 3.3V and 5.0V pASIC? 2 FPGA Combining Speed, Density, Low Cost and Flexibility |
| 中文描述： | 3.3V和5.0V帕希奇？ 2 FPGA的结合速度，密度，低成本和灵活性 |
| 文件页数： | 10/12页 |
| 文件大小： | 272K |
| 代理商： | QL2009-XPQ208C |
QL2009
3-44
AC CHARACTERISTICS at VCC = 5V, TA = 25
°
C (K = 1.00)
Propagation delays depend on routing, fanout, load capacitance, supply voltage, junction temperature,
and process variation. The AC Characteristics are a design guide to provide initial timing estimates at
nominal conditions. Worst case estimates are obtained when nominal propagation delays are multiplied
by the appropriate Delay Factor, K, as specified in the Delay Factor table (Operating Range). The
Quick
Chip
/Quick
Tools
/Quick
Works
software incorporates data sheet AC Characteristics into the
design database for precise path analysis or simulation results following place and route.
Logic Cells
Input-Only Cells
Symbol
Parameter
Propagation Delays (ns)
Fanout
[8]
2
3
2.6
2.6
2.7
2.7
2.7
2.8
4.8
4.8
0.0
0.0
1.0
1.0
1.1
0.9
0.9
4.1
4.1
0.0
0.0
1
4
8
12
4.6
4.7
4.8
0.0
3.0
2.9
4.1
0.0
24
5.8
5.9
4.8
0.0
4.2
4.1
4.1
0.0
tIN
tINI
tISU
tIH
tlCLK
tlRST
tlESU
tlEH
High Drive Input Delay
High Drive Input, Inverting Delay
Input Register Set-Up Time
Input Register Hold Time
Input Register Clock To Q
Input Register Reset Delay
Input Register clock Enable Set-Up Time
Input Register Clock Enable Hold Time
2.5
2.6
4.8
0.0
0.9
0.8
4.1
0.0
3.5
3.6
4.8
0.0
1.9
1.8
4.1
0.0
4.8
0.0
1.0
4.1
0.0
Notes:
[8]
Stated timing for worst case Propagation Delay over process variation at VCC=5.0V and TA=25
°
C.
Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as
specified in the Operating Range.
These limits are derived from a representative selection of the slowest paths through the pASIC 2 logic
cell
including typical net delays
. Worst case delay values for specific paths should be determined from
timing analysis of your particular design.
[9]
Symbol
Parameter
Propagation Delays (ns)
Fanout
[8]
2
1.7
2.0
1.8
1.8
0.0
0.0
1.1
1.4
2.0
2.0
2.0
2.0
1.7
2.0
1.5
1.8
1.9
1.9
1.8
1.8
1
3
4
8
tPD
tSU
tH
tCLK
tCWHI
tCWLO
tSET
tRESET
tSW
tRW
Combinatorial Delay [9]
Setup Time [9]
Hold Time
Clock to Q Delay
Clock High Time
Clock Low Time
Set Delay
Reset Delay
Set Width
Reset Width
1.4
1.8
0.0
0.8
2.0
2.0
1.4
1.2
1.9
1.8
2.3
1.8
0.0
1.7
2.0
2.0
2.3
2.1
1.9
1.8
3.5
1.8
0.0
2.9
2.0
2.0
3.5
3.3
1.9
1.8
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