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参数资料
| 型号： | QL3060-4PQ208I |
| 英文描述： | FPGA|1584-CELL|CMOS|QFP|208PIN|PLASTIC |
| 中文描述： | FPGA的| 1584细胞|的CMOS | QFP封装| 208PIN |塑料 |
| 文件页数： | 8/10页 |
| 文件大小： | 181K |
| 代理商： | QL3060-4PQ208I |
7-53
QL3060 - pASIC 3 FPGATM
Pin Descriptions
Ordering Information
PIN DESCRIPTIONS
Pin
Function
Description
TDI
Test Data In for JTAG
Hold HIGH during normal operation. Connect to
VCC if not used for JTAG.
TRSTB
Active low Reset for JTAG
Hold LOW during normal operation. Connect to
ground if not used for JTAG.
TMS
Test Mode Select for JTAG
Hold HIGH during normal operation. Connect to
VCC if not used for JTAG.
TCK
Test Clock for JTAG
Hold HIGH or LOW during normal operation.
Connect to VCC or ground if not used for JTAG.
TDO
Test data out for JTAG
Output that must be left unconnected if not used for
JTAG.
STM
Special Test Mode
Must be grounded during normal operation.
I/ACLK
High-drive input and/or
array network driver
Can be configured as either or both.
I/GCLK
High-drive input and/or
global network driver
Can be configured as either or both.
I
High-drive input
Use for input signals with high fanout.
I/O
Input/Output pin
Can be configured as an input and/or output.
VCC
Power supply pin
Connect to 3.3V supply.
VCCIO
Input voltage tolerance pin
Connect to 5.0 volt supply if 5 volt input tolerance is
required, otherwise connect to 3.3V supply.
GND
Ground pin
Connect to ground.
QL 3060 - 1 PQ208 C
QuickLogic
pASIC device
Speed Grade
0 = quick
1 = fast
2 = faster
3 = faster
*4 = fastest
Package Code
PQ208 = 208-pin PQFP
PB456 = 456-pin PBGA
pASIC 3 device
part number
Operating Range
C = Commercial
I = Industrial
M = Military
* Contact QuickLogic regarding availability
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