- 您现在的位置：买卖IC网 > PDF目录361286 > QL3060 (QuickLogic Corp.) pASIC3 FPGA Combining High Performance and High Density(高性能和高密度相结合的pASIC3现场可编程门阵列) PDF资料下载
参数资料
| 型号： | QL3060 |
| 厂商： | QuickLogic Corp. |
| 英文描述： | pASIC3 FPGA Combining High Performance and High Density(高性能和高密度相结合的pASIC3现场可编程门阵列) |
| 中文描述： | pASIC3 FPGA的结合高性能和高密度（高性能和高密度相结合的pASIC3现场可编程门阵列） |
| 文件页数： | 8/14页 |
| 文件大小： | 239K |
| 代理商： | QL3060 |
30
Preliminary
8-30
Military Plastic pASIC 3 Family
QL3025
AC CHARACTERISTICS at VCC = 3.3V, TA = 25
°
C (K = 1.00)
(To calculate delays, multiply the appropriate K factor in the "Operating Range" section by the following numbers.)
Logic Cells
Input-Only/Clock Cells
Notes:
[5] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25
°
C. Multi-
ply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the
Operating Range.
[6] These limits are derived from a representative selection of the slowest paths through the pASIC 3 logic cell
including typical net delays. Worst case delay values for specific paths should be determined from timing
analysis of your particular design.
QL3025
Symbol
Parameter
Propagation Delays (ns)
Fanout
[5]
2
1.7
1.9
1.7
1.7
0.0
0.0
1.0
1.2
1.2
1.2
1.2
1.2
1.3
1.5
1.1
1.3
1.9
1.9
1.8
1.8
1
3
4
8
tPD
tSU
tH
tCLK
tCWHI
tCWLO
tSET
tRESET
tSW
tRW
Combinatorial Delay [6]
Setup Time [6]
Hold Time
Clock to Q Delay
Clock High Time
Clock Low Time
Set Delay
Reset Delay
Set Width
Reset Width
1.4
1.7
0.0
0.7
1.2
1.2
1.0
0.8
1.9
1.8
2.2
1.7
0.0
1.5
1.2
1.2
1.8
1.6
1.9
1.8
3.2
1.7
0.0
2.5
1.2
1.2
2.8
2.6
1.9
1.8
Symbol
Parameter
Propagation Delays (ns)
Fanout
[5]
2
3
1.6
1.8
1.9
1.7
1.9
2.0
3.1
3.1
3.1
0.0
0.0
0.0
0.8
1.0
1.1
0.7
0.9
1.0
2.3
2.3
2.3
0.0
0.0
0.0
1
4
8
12
2.9
3.0
3.1
0.0
2.1
2.0
2.3
0.0
24
4.4
4.5
3.1
0.0
3.6
3.5
2.3
0.0
tIN
tINI
tISU
tIH
tlCLK
tlRST
tlESU
tlEH
High Drive Input Delay
High Drive Input, Inverting Delay
Input Register Set-Up Time
Input Register Hold Time
Input Register Clock To Q
Input Register Reset Delay
Input Register clock Enable Set-Up Time
Input Register Clock Enable Hold Time
1.5
1.6
3.1
0.0
0.7
0.6
2.3
0.0
2.4
2.5
3.1
0.0
1.6
1.5
2.3
0.0
相关PDF资料 |
PDF描述 |
|---|---|
| QL3025 | pASIC3 FPGA Combining High Performance and High Density(高性能和高密度相结合的pASIC3现场可编程门阵列) |
| QL4009-3PF84C | CONV DC/DC 10W DUL 5V +-12V PCB |
| QL4009-3PF84I | 9,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM |
| QL4009-3PF84M | 9,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM |
| QL4009-3PL68C | 9,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| QL3060-0PB456C | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA|1584-CELL|CMOS|BGA|456PIN|PLASTIC |
| QL3060-0PB456I | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| QL3060-0PL84M | 制造商:未知厂家 制造商全称:未知厂家 功能描述:60,000 Usable PLD Gate pASIC3 FPGA Combining High Performance and High Density |
| QL3060-0PQ208C | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA|1584-CELL|CMOS|QFP|208PIN|PLASTIC |
| QL3060-0PQ208I | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
发布紧急采购，3分钟左右您将得到回复。