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参数资料
| 型号： | QL4016-0CF100C |
| 厂商： | QUICKLOGIC CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 320 CLBS, 61280 GATES, CQFP100 |
| 封装： | CERAMIC, QFP-100 |
| 文件页数： | 1/45页 |
| 文件大小： | 1332K |
| 代理商： | QL4016-0CF100C |
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2007 QuickLogic Corporation
1
Device Highlights
High Performance & High Density
Up to 90,000 usable PLD gates with up to
316 I/Os
300 MHz 16-bit counters, 400 MHz datapaths,
160+ MHz FIFOs
0.35 m four-layer metal non-volatile CMOS
process
High Speed Embedded SRAM
Up to 22 dual-port RAM modules, organized in
user-configurable 1,152 bit blocks
5 ns access times, each port independently
accessible
Fast and efficient for FIFO, RAM, and ROM
functions
Easy to Use/Fast Development
Cycles
100% routable with 100% utilization and
complete pin-out stability
Variable-grain logic cells provide high
performance and 100% utilization
Comprehensive design tools include high quality
Verilog/VHDL synthesis
Advanced I/O Capabilities
Interfaces with 3.3 V and 5.0 V devices
PCI compliant with 3.3 V and 5.0 V busses for
-1/-2/-3/-4 speed grades
Full JTAG boundary scan
I/O cells with individually controlled registered
input path and output enables
Up to 316 I/O Pins
Up to 308 bi-directional input/output pins,
PCI-compliant for 5.0 V and 3.3 V buses for
-1/-2/-3/-4 speed grades
Eight high-drive input/distributed network pins
Eight Low-Skew Distributed
Networks
Two array clock/control networks are available to
the logic cell flip-flop; clock, set, and reset inputs
— each can be driven by an input-only pin
Six global clock/control networks available to the
logic cell; F1, clock, set, and reset inputs and the
data input, I/O register clock, reset, and enable
inputs as well as the output enable control—each
can be driven by an input-only, I/O pin, any logic
cell output, or I/O cell feedback
High Performance Silicon
Input + logic cell + output total delays under 6 ns
Data path speeds over 400 MHz
Counter speeds over 300 MHz
FIFO speeds over 160+ MHz
Figure 1: QuickRAM Block Diagram
22
RAM
Blocks
1,58 4
Hi gh S peed
Logic Cells
Interface
QuickRAM Family Data Sheet
QuickRAM ESP Combining Performance, Density and
Embedded RAM
相关PDF资料 |
PDF描述 |
|---|---|
| QL4016-0CF100I | FPGA, 320 CLBS, 61280 GATES, CQFP100 |
| QL4016-0PF100C | FPGA, 320 CLBS, 61280 GATES, PQFP100 |
| QL4016-0PF100I | FPGA, 320 CLBS, 61280 GATES, PQFP100 |
| QL4016-0PF144C | FPGA, 320 CLBS, 61280 GATES, PQFP144 |
| QL4016-0PF144I | FPGA, 320 CLBS, 61280 GATES, PQFP144 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| QL4016-0CF100I | 制造商:未知厂家 制造商全称:未知厂家 功能描述:16,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM |
| QL4016-0CF100M | 制造商:未知厂家 制造商全称:未知厂家 功能描述:16,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM |
| QL4016-0CF100M/883 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:90,000 Usable PLD Gate QuickRAM Combining Performance, Density and Embedded RAM |
| QL4016-0CF208M | 制造商:未知厂家 制造商全称:未知厂家 功能描述:90,000 Usable PLD Gate QuickRAM Combining Performance, Density and Embedded RAM |
| QL4016-0CF208M/883 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:90,000 Usable PLD Gate QuickRAM Combining Performance, Density and Embedded RAM |
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