- 您现在的位置：买卖IC网 > PDF目录361292 > QL5064-33APB456I BUS CONTROLLER PDF资料下载
参数资料
| 型号： | QL5064-33APB456I |
| 英文描述： | BUS CONTROLLER |
| 中文描述： | 总线控制器 |
| 文件页数： | 11/37页 |
| 文件大小： | 806K |
| 代理商： | QL5064-33APB456I |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页当前第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页
QL5064 QuickPCI Data Sheet Rev D
11
QL5064 QuickPCI Data Sheet
11.0 Control_Data Bus Descripiton
The Control_DATA bus is the heart of the control circuitry for the PCI interface. The intent of this bus is to provide
access to all of the control structures necessary for a microprocessor interfaced to the QL5064 device to be able
to marshal all PCI operations. This bus, like the DataIN and DataOUT busses is synchronous to user_clk, and can
be written or read on every clock. This is a bi-directional bus, offering both read and write access at 64-bits. In
addition to all control structures, this bus is designed to access all of the six FIFOs.
12.0 PCI Master Arbitration
Five possible masters could be driving PCI master transactions on the PCI bus, and as a result, a flexible
arbitration controller has been included in the QL5064 device. The five sources for PCI master
transactions include: Transmit FIFO 0, Transmit FIFO 1, Receive FIFO 0, Receive FIFO 1, and SPCI
(Single PCI Access). (SPCI is a means for the back end-design to initiate single quad-word transfers
directly on the PCI bus for master transactions, bypassing the DMA FIFOs). SPCI Mastering is controlled
through the Control_DATA bus.
Three arbitration modes have been defined for the QL5064 device. These are round robin, prioritized,
and customized. In all modes, the SPCI Mastering always has highest priority. The arbitration scheme
is selected by setting the proper values in the Arbitration Mode bits of configuration registers (offset
0xD0, bits 49:48). The selection is: 00b - round robin, 01b - prioritized, 10b - customized, 11b -
reserved.
Round robin arbitration simply cycles through the four Master FIFOs in the following order: Transmit 0
(T0), Transmit 1 (T1), Receive 0 (R0), Receive 1 (R1). Prioritized mode uses values assigned to
DMA_arbitration_priority bits in the configuration memory (offset 0xD0). Masters set to equal priority
are arbitrated (high to low): T0, T1, R0, R1.
Customized arbitration mode uses two busses and back-end logic. The fpga_bus_req[3:0] signals (1 bit
per FIFO) indicate to the programmable logic design which master is requesting the bus. The
fpga_bus_req bits are assigned: [0]-R1, [1]-R0, [2]-T1, [3]-T0. The back-end design should set
fpga_arb_sel[1:0] according to which master should be granted the bus. The fpga_arb_sel bus uses the
enumeration: 00-R1, 01-R0, 10-T1, 11-T0.
相关PDF资料 |
PDF描述 |
|---|---|
| QL5064-33APB484C | BUS CONTROLLER |
| QL5064-33APB484I | BUS CONTROLLER |
| QL5064-33BPB456C | BUS CONTROLLER |
| QL5064-33BPB456I | BUS CONTROLLER |
| QL5064-33BPB484C | BUS CONTROLLER |
相关代理商/技术参数 |
参数描述 |
|---|---|
| QL5064-66APS484C-5541 | 制造商:QuickLogic Corporation 功能描述: |
| QL5064-66APS484I-5541 | 制造商:QuickLogic Corporation 功能描述: |
| QL5064-66BPS484C-5725 | 制造商:QuickLogic Corporation 功能描述: |
| QL5064-75CPS484C-5616 | 制造商:QuickLogic Corporation 功能描述: |
| QL5064-75CPS484I-5612 | 制造商:QuickLogic Corporation 功能描述: |
发布紧急采购，3分钟左右您将得到回复。