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参数资料
| 型号： | QL5064-33APB484C |
| 英文描述： | BUS CONTROLLER |
| 中文描述： | 总线控制器 |
| 文件页数： | 7/37页 |
| 文件大小： | 806K |
| 代理商： | QL5064-33APB484C |
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QL5064 QuickPCI Data Sheet Rev D
7
QL5064 QuickPCI Data Sheet
6.0 Mailbox Registers and I
2
O
The PCI interface contains 16 bytes of mailbox registers to support message/semaphore passing
between the programmable logic design and the PCI bus. These mailbox registers are memory mapped
to a dedicated register bank within the first 256 bytes of BAR 0. 8 bytes are provided for the FPGA to
PCI direction, and 8 bytes are also provided for the PCI to FPGA direction. Status flags and interrupts
are available for each direction as well. Figure 4 below shows the mailbox structure within the QL5064
device. Hardware controlled queues allow full I
2
O messaging support with a processor and local I
2
O
drivers.
Figure 4: Mailbox Structure
full interrupt
empty interrupt
63 0
byte 7
byte 6
byte 5
byte 4
byte 3
byte 2
byte 1 byte 0
63 0
byte 7
byte 6
byte 5
byte 4
byte 3
byte 2
byte 1 byte 0
STATUS REGISTER
INTERRUPT CONTROL
interrupt
configuration
register
INTERRUPT CONTROL
8
empty interrupt
PCI BUS
CNTL
BUS
STATUS REGISTER
status
8
outgoing
decode
control
incoming
decode
control
status
status
status
full interrupt
mailbox 7
mailbox 5
User Outgoing mailboxes
mailbox 3
mailbox 1
mailbox 6
mailbox 4
mailbox 2
mailbox 0
interrupt
configuration
register
相关PDF资料 |
PDF描述 |
|---|---|
| QL5064-33APB484I | BUS CONTROLLER |
| QL5064-33BPB456C | BUS CONTROLLER |
| QL5064-33BPB456I | BUS CONTROLLER |
| QL5064-33BPB484C | BUS CONTROLLER |
| QL5064-33BPB484I | BUS CONTROLLER |
相关代理商/技术参数 |
参数描述 |
|---|---|
| QL5064-66APS484C-5541 | 制造商:QuickLogic Corporation 功能描述: |
| QL5064-66APS484I-5541 | 制造商:QuickLogic Corporation 功能描述: |
| QL5064-66BPS484C-5725 | 制造商:QuickLogic Corporation 功能描述: |
| QL5064-75CPS484C-5616 | 制造商:QuickLogic Corporation 功能描述: |
| QL5064-75CPS484I-5612 | 制造商:QuickLogic Corporation 功能描述: |
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