参数资料
型号: QL6250PT280
英文描述: ASIC
中文描述: 专用集成电路
文件页数: 2/13页
文件大小: 165K
代理商: QL6250PT280
2
www.quicklogic.com
2001 QuickLogic Corporation
Eclipse Family Data Sheet
1.1 QuickWorks Design Software
The turnkey QuickWorks package provides the most complete ESP and FPGA software solution from
design entry to logic synthesis, to place and route to simulation. The packages provide a solution for
designers who use third party tools from Cadence, Mentor, OrCAD, Synopsys, Viewlogic and other
third-party tools for design entry, synthesis, or simulation.
1.2 Process Data
Eclipse is fabricated on a .25um 5 layer metal CMOS process. The core voltage is 2.5 V Vcc supply and
3.3 tolerant I/O with the addition of 3.3 V Vccio. Eclipse is available in commercial, industrial, and
military temperature grades.
1.3 Programmable Logic Architectural Overview
The Eclipse features an enhanced Supercell with an additional D flip-flop register and associated control
logic. This advanced architectural approach, addresses today's highly register intensive designs.
Table 1: Eclipse Product Family Members
QL6250
QL6325
QL6500
QL6600
Max Gates
248,160
320,640
488,064
583,008
Logic Array
40x24
48x32
64x48
72x56
Logic Cells
960
1,536
3,072
4,032
Max Flip-Flops
2,688
4,302
7,488
9,600
Max I/O
256
320
448
512
RAM Modules
20
24
32
36
RAM bits
46,100
55,300
73,700
82,900
Packages
PQFP
208
208
BGA (1.27mm)
516
516
516
516
BGA (1.0mm)
484
484
484, 672
484, 672
FPBGA (0.8mm)
280
280
280
280
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