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参数资料
| 型号： | QL6325PQ208 |
| 英文描述： | ASIC |
| 中文描述： | 专用集成电路 |
| 文件页数： | 5/13页 |
| 文件大小： | 165K |
| 代理商： | QL6325PQ208 |
Eclipse
TM
Family Data Sheet
5
Eclipse Family Data Sheet
The Write Enable (WE) line acts as a clock enable for synchronous write operation. The Read Enable
(RE) acts as a clock enable for synchronous READ operation (ASYNCRD input low), or as a flow-through
enable for asynchronous READ operation (ASYNCRD input high).
Designers can cascade multiple RAM modules to increase the depth or width allowed in single modules
by connecting corresponding address lines together and dividing the words between modules.
A similar technique can be used to create depths greater than 512 words. In this case address signals
higher than the ninth bit are encoded onto the write enable (WE) input for WRITE operations. The READ
data outputs are multiplexed together using encoded higher READ address bits for the multiplexer
SELECT signals.
The RAM blocks can be loaded with data generated internally (typically for RAM or FIFO functions) or
with data from an external PROM (typically for ROM functions). The RAM achieve 155 MHz
performance for the lowest speed grade devices when using multiple blocks cascaded together.
2.1 Multiple Accessing of Memories
The extremely fast RAM can be used in designs that require multiple memory accessing. The RAM
achieves 280 MHz performance for the fastest speed grade and 155 MHz performance for the lowest
speed grade devices when using multiple blocks cascaded together. Write through of DATA is also
possible with the QuickLogic RAM.
3.0 I/O Cell Structure
Eclipse features a variety of distinct I/O pins to maximize performance, functionality, and flexibility with
bi-directional I/O pins and input-only pins. All input and I/O pins are 2.5V and 3.3V tolerant and
comply with the specific I/O standard selected. The outputs swing from Vss to VCCI/O (0V to 3.3V ±
10%). The VCCI/O pins must be tied to a 3.3V supply to provide 3.3V compliance. If 3.3V compliance
is not required, then these pins must be tied to the 2.5V supply. Eclipse can also support LVDS and
LVPECL I/O standards with the addition of an external resistor. Table 3 summarizes the I/O
specifications that will be supported.
As designs become more complex and requirements more stringent, varying I/O standards are
developing for specific applications. I/O standards for processors, memories and various bus
applications have become common place and a requirement for many systems. In addition, I/O timing
has become a greater issue with specific requirements for setup, hold, clock to out, and switching times.
Table 3: I/O Standards and Applications
I/O Standard Reference Voltage Output Voltage
Application
LVTTL
n/a
3.3
General Purpose
LVCMOS2
n/a
2.5
General Purpose
PCI
n/a
3.3
PCI Bus Applications
GTL+
1
n/a
High Speed Bus - Pentium Pro
SSTL3
1.5
3.3
Memory Bus - Hitachi, IBM
SSTL2
1.25
2.5
Memory Bus - Hitachi, IBM
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