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| 型号： | QL6600PB516 |
| 英文描述： | ASIC |
| 中文描述： | 专用集成电路 |
| 文件页数： | 10/13页 |
| 文件大小： | 165K |
| 代理商： | QL6600PB516 |
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2001 QuickLogic Corporation
Eclipse Family Data Sheet
5.3 Dedicated Clock
There is one dedicated clock in the Eclipse device family. It connects to the clock input of the SuperCell,
I/O and RAM registers through a hardwired connection and is multiplexed with the programmable clock
input. There are four inversions from pad to register inputs and the dedicated clock takes on the same
configuration as the global clock. The dedicated clock provides a fast global network with low skew. You
have the ability to select either the dedicated clock or the programmable clock, Figure 9. The
performance of the dedicated clock is given in Table 5.
Figure 9: Dedicated Clock Circuitry within Logic Cell
5.4 I/O Control and Local Hi-Drives
Each bank of I/O's has 2 input only pins that can be programmed to drive the RST, CLK and EN inputs
of I/O's in that bank. These input only pins also double up as high drive inputs to a quadrant. Both as
an I/O control or high drive, these buffers can be driven by the internal logic. The performance is
indicated in Table 6.
Table 5: Dedicated Clock Performance
Clock Performance
TT, 25C, 2.5V
Global
Dedicated
Macro (near)
1.51 ns
1.59 ns
I/O (far)
2.06 ns
1.73 ns
Skew
0.55 ns
0.14 ns
Table 6: I/O Control Network/Local High-Drive
TT, 25C, 2.5V
From Pad
From Array
I/O (slow)
1.00ns
1.14ns
I/O (fast)
0.63ns
0.78ns
Skew
0.37ns
0.36ns
CLK
Programmable clock
Hard-wired clock
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