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| 型号： | QL6600PS484 |
| 英文描述： | ASIC |
| 中文描述： | 专用集成电路 |
| 文件页数： | 6/13页 |
| 文件大小： | 165K |
| 代理商： | QL6600PS484 |
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www.quicklogic.com
2001 QuickLogic Corporation
Eclipse Family Data Sheet
The Eclipse family has addressed these changing system requirements. The Eclipse family includes a
completely new I/O cell which consists of programmable I/Os as well as a new cell structure consisting
of 3 registers - input, output and output enable. Eclipse will offer banks of programmable I/O that
addresses many of the new bus standards that are popular today. In addition, the input register addresses
the setup time; the output register addresses clock-to-out time; and the OE register addresses the
switching time from high impedance to a given value.
Figure 5: Eclipse I/O Cell
The bi-directional I/O pin options can be programmed for input, output, or bi-directional operation. As
shown in Figure 5, each bi-directional I/O pin is associated with an I/O cell which features an
input/feedback register, an input buffer, output/feedback register, three-state output buffer, an output
enable register, and two (2) two-to-one multiplexers.
For input functions, I/O pins can provide combinatorial, registered data or both options simultaneously
to the logic array. For combinatorial input operation, data is routed from I/O pins through the input
buffer to the array logic. For registered input operation, I/O pins drive the D input of input cell registers,
allowing data to be captured with fast set-up times without consuming internal logic cell resources.
For output functions, I/O pins can receive combinatorial or registered data from the logic array. For
combinatorial output operation, data is routed from the logic array through a multiplexer to the I/O pin.
For registered output operation, the array logic drives the D input of the output cell register which in
turn drives the I/O pin through a multiplexer. The multiplexer allows either a combinatorial or a
registered signal to be driven to the I/O pin.
The three-state output buffer controls the flow of data from the array logic to the I/O pin and allows the
I/O pin to act as an input and/or output. The buffer's output enable can be individually controlled by a
logic cell array or any pin (through the regular routing resources), or bank-controlled through one of the
global networks. The signal can be also be either combinatorial or registered. This is identical to that of
the flow for the output cell. For combinatorial control operation data is routed from the logic array
through a multiplexer to the three-state control. For registered control operation, the array logic drives
the D input of the OE cell register which in turn drives the three-state control through a multiplexer. The
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