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参数资料
| 型号： | QL7100-5PS484M |
| 英文描述： | USER PROGRAMMABLE SPECIAL FUNCTION ASIC|CMOS|BGA|484PIN |
| 中文描述： | 用户可编程特殊功能的ASIC |的CMOS | BGA封装| 484PIN |
| 文件页数： | 13/24页 |
| 文件大小： | 268K |
| 代理商： | QL7100-5PS484M |
QL7100 QuickDSP
TM
Data Sheet Rev A
13
QL7100 QuickDSP Data Sheet
4.0 Pin Descriptions
Table 14: Pin Descriptions
Pin
Function
Description
TDI/RSI
Test Data In for JTAG /RAM init.
Serial Data In
Hold HIGH during normal operation. Connects to serial PROM data in for
RAM initialization. Connect to VCC if unused
TRSTB/RRO
Active low Reset for JTAG /RAM
init. reset out
Hold LOW during normal operation. Connects to serial PROM reset for
RAM initialization. Connect to GND if unused
TMS
Test Mode Select for JTAG
Hold HIGH during normal operation. Connect to VCC if not used for JTAG
TCK
Test Clock for JTAG
Hold HIGH or LOW during normal operation. Connect to VCC or ground
if not used for JTAG
TDO/RCO
Test data out for JTAG /RAM init.
clock out
Connect to serial PROM clock for RAM initialization. Must be left
unconnected if not used for JTAG or RAM initialization
I/GCLK
High-drive input and/or global
network driver
Can be configured as either or both
I/O
Input/Output pin
Can be configured as an input and/or output
VCC
Power supply pin
Connect to 2.5V supply
VCCIO
Input voltage tolerance pin
Connect to 3.3 volt supply if 3.3 volt input tolerance is required, otherwise
connect to 2.5V supply
GND
Ground pin
Connect to ground
PLLIN
PLL clock input
Clock input for PLL
DEDCLK
Dedicated clock pin
Low skew global clock
GNDPLL
Ground pin for PLL
Connect to GND
INREF
Differential reference voltage
Connect to reference voltage or ground if used for non-differential input
PLLOUT
PLL output pin
Dedicated PLL output pin. Otherwise may be left unconnected
IOCTRL
Highdrive input
Can be used as highdrive input or clock to I/O register within the same
bank. Tied low or high if unused
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