参数资料
型号: QL7100-6PS484M
英文描述: USER PROGRAMMABLE SPECIAL FUNCTION ASIC|CMOS|BGA|484PIN
中文描述: 用户可编程特殊功能的ASIC |的CMOS | BGA封装| 484PIN
文件页数: 9/24页
文件大小: 268K
代理商: QL7100-6PS484M
QL7100 QuickDSP
TM
Data Sheet Rev A
9
QL7100 QuickDSP Data Sheet
Figure 13: QuickDSP Input Register Cell Timing
Table 7: Standard Input Delays
Symbol
Parameter
Propagation
delay (ns)
Standard
Input Delays
To get the total input delay and this delay to tISU
1
tSID (LVTTL)
LVTTL input delay: Low Voltage TTL for 3.3V applications
0.34
tSID (LVCMOS2)
LVCMOS2 input delay: Low Voltage CMOS for 2.5V and lower
applications
0.42
tSID (GTL+)
GTL+ input delay: Gunning Transceiver Logic
0.68
tSID (SSTL3)
SSTL3 input delay: Stub Series Terminated Logic for 3.3V
0.55
tSID (SSTL2)
SSTL2 input delay: Stub Series Terminated Logic for 2.5V
0.607
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