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| 型号： | QL7100-6PT280I |
| 英文描述： | USER PROGRAMMABLE SPECIAL FUNCTION ASIC|CMOS|BGA|280PIN |
| 中文描述： | 用户可编程特殊功能的ASIC |的CMOS | BGA封装| 280PIN |
| 文件页数： | 14/24页 |
| 文件大小： | 268K |
| 代理商： | QL7100-6PT280I |
14
www.quicklogic.com
2001 QuickLogic Corporation
QL7100 QuickDSP Data Sheet
4.1 Recommended Unused Pin Terminations for the QuickDSP devices
All unused, general purpose I/O pins can be tied to VCC, GND or HIZ (high impedance) internally using
the Configuration Editor. The option is given in the right-bottom corner of the Configuration window.
The use the Configuration Editor go to: TOOLS/CONFIGURATION PINS.
The rest of the pins should be terminated at the board level in the following manner:
NOTE:
x -> number, y -> alphabetical character
Figure 16: Ordering Information
Table 15: Recommended Unused Pin Terminations
Signal Name
Recommended Termination
PLLOUT<x>
Unused PLL output pins must be connected to either VCC or GND so that their associated input
buffer never floats. Utilized PLL output pins that route the PLL clock outside of the chip, do not need
to be tied to either VCC or GND.
IOCTRL<y>
Any unused pins of this type must be connected to either VCC or GND.
CLK/PLLIN<x>
Any unused clock pins should be connected to VCC or GND.
PLLRST<x>
If a PLL module is not used, then the associated PLLRST<x> must be connected to VCC, under
normal operation use it as needed.
INREF<y>
If an I/O bank does not require the use of INREF signal the pin should be connected to GND.
QL 7100 - 4 PS672 C
QuickLogic device
QuickDSP device
part number
Speed Grade
4 = Quick
5 = Fast
6 = Faster
7 = Fastest
Operating Range
C = Commercial
I = Industrial
M = Military
Package Code
PT280 = 280-pin FPBGA
PS484 = 484-pin BGA (1.0mm)
PS672 = 672-pin BGA (1.0mm)
PB516 = 516-pin BGA (1.27mm)
相关PDF资料 |
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| QL7100-6PT280M | USER PROGRAMMABLE SPECIAL FUNCTION ASIC|CMOS|BGA|280PIN |
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| QL7100-4PB516C | USER PROGRAMMABLE SPECIAL FUNCTION ASIC|CMOS|BGA|516PIN |
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