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参数资料
| 型号： | QL7180-5PS484I |
| 英文描述： | USER PROGRAMMABLE SPECIAL FUNCTION ASIC|CMOS|BGA|484PIN |
| 中文描述： | 用户可编程特殊功能的ASIC |的CMOS | BGA封装| 484PIN |
| 文件页数： | 8/26页 |
| 文件大小： | 315K |
| 代理商： | QL7180-5PS484I |
8
www.quicklogic.com
2001 QuickLogic Corporation
QL7180 DSP Data Sheet
Figure 12: QuickDSP Input Register Cell
Table 6: Input Register Cell
Symbol
Parameter
Propagation
delay (ns)
Input Register Cell Only
1
tISU
Input register setup time: the amount of time the synchronous input of
the flip flop must be stable before the active clock edge
3.12
tIH
Input register hold time: the amount of time the synchronous input of the
flip flop must be stable after the active clock edge
0
tICLK
Input register clock to Q: the amount of time taken by the flip flop to
output after the active clock edge
1.08
tIRST
Input register reset delay: amount of time between when the flip flop is
“reset”(low) and when Q is consequently “reset” (low)
0.99
tIESU
Input register clock enable setup time: the amount of time “enable” must
be stable before the active clock edge
0.37
tIEH
Input register clock enable time: the amount of time “enable” must be
stable after the active clock edge
0
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