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参数资料
| 型号： | QLX4300SIQT7 |
| 厂商： | Intersil |
| 文件页数： | 7/21页 |
| 文件大小： | 0K |
| 描述： | IC EQUALIZER REC 3.125GBPS 46QFN |
| 标准包装： | 1 |
| 系列： | QLx™ |
| 应用： | 数据传输 |
| 电源电压： | 1.1 V ~ 1.3 V |
| 封装/外壳： | 46-WFQFN 裸露焊盘 |
| 供应商设备封装： | 46-TQFN |
| 包装： | 标准包装 |
| 安装类型： | 表面贴装 |
| 其它名称： | QLX4300SIQT7-DKR QLX4300SIQT7-DKR-ND QLX4300SIQT7DKR |
15
FN6982.1
November 19, 2009
Serial Bus Programming
Pins 16 (DI), 45 (ENB), and 46 (CLK) are used to
program the registers inside the QLx4300-S45. Figure 22
shows an exemplary timing diagram for the signals on
these pins. The serial bus can be used to program a
single QLx4300-S45 according to the following steps:
1. The ENB pin is pulled ‘LOW’.
- While this pin is ‘LOW’, the data input on DI are
read into registers but not yet latched.
- A setup time of tSCK is needed between ENB going
‘LOW’ and the first rising clock edge.
2. At least 21 values are read from DI on the rising
edge of the CLK signal.
- If more than 21 values are passed in, then only the
last 21 values are kept in a FIFO fashion.
- The data on DI should start by sending the value
destined for register 21 and finish by sending the
value destined for register 1.
- A range of clock frequencies can be used. A typical
rate is 10MHz. The clock should not exceed 20MHz.
-Setup (tSDI) and hold (tHDI) times are needed
around the rising clock edge.
3. The ENB pin is pulled ‘HIGH’ and the contents of the
registers are latched and take effect.
- After clocking in the last data bit, an additional
tHEN should elapse before pulling the ENB signal
‘HIGH’.
- After completing these steps, the new values will
affect within tD.
Programming Multiple QLx4300-S45
Devices
The serial bus interface provides a simple means of
setting the equalizer boost levels with a minimal amount
of board circuitry. Many of the serial interface signals can
be shared among the QLx4300-S45 devices on a board
and two options are presented in this section. The first
uses common clock and serial data signals along with
separate ENB signals to select which QLx4300-S45
accepts the programmed changes. The second method
uses a common ENB signal as the serial data is
carried-over from one QLx4300-S45 to the next.
Separate ENB Signals
Multiple QLx4300-S45 devices can be programmed from
a common serial data stream as shown in Figure 23.
Here, each QLx4300-S45 is provided its own ENB signal,
and only one of these ENB signals is pulled ‘LOW’, and
hence accepting the register data one at a time. In this
situation, the programming of each equalizer follows the
steps outlined in Figure 22.
DI/DO Carryover
The DO pin (pin 17) can be used to daisy-chain the serial
bus among multiple QLx4300-S45 chips. The DO pin
outputs the overflow data from the DI pin. Specifically, as
data is pipelined into a QLx4300-S45, it proceeds
according to the following flow. First, a bit goes into
shadow register 1. Then, with each clock cycle, it shifts
over into subsequent higher numbered registers. After
shifting into register 21, it is output on the DO pin on the
same clock cycle. Thus, the DO signal is equal to the DI
signal, but delayed by 20 clock cycles. The timing
diagram for the DO pin is shown in Figure 24 where the
first 20 bits output from the DO are indefinite and
subsequent bits are the data fed into the DI pin. The
delay between the rising clock edge and the data
transition is tCQ.
A diagram for programming multiple QLx4300-S45s is
shown in Figure 25. It is noted that the board layout
should ensure that the additional clock delay experienced
between subsequent QLx4300-S45s should be no more
than the minimum value of tCQ, i.e. 12ns.
FIGURE 22. TIMING DIAGRAM FOR PROGRAMMING THE INTERNAL REGISTERS OF THE QLx4300-S45
R21
R20
R19
R1
tSDI tHDI
tSCK
tHEN
DI
CLK
ENB
QLx4300-S45
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相关代理商/技术参数 |
参数描述 |
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| QLX4600LIQSR | 功能描述:接口 - 专用 6 GBS QD CH LANE EXTENDER RoHS:否 制造商:Texas Instruments 产品类型:1080p60 Image Sensor Receiver 工作电源电压:1.8 V 电源电流:89 mA 最大功率耗散: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:BGA-59 |
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